src/soc/intel/xeon_sp/skx/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config SOC_INTEL_SKYLAKE_SP
   4         bool
   5         select XEON_SP_COMMON_BASE
   6         select PLATFORM_USES_FSP2_0
   7         select NO_FSP_TEMP_RAM_EXIT
   8         select UDK_202005_BINDING
   9         select HAVE_X86_64_SUPPORT
  10         select USE_X86_64_SUPPORT
  11         help
  12           Intel Skylake-SP support
  13
  14 if SOC_INTEL_SKYLAKE_SP
  15
  16 config FSP_HEADER_PATH
  17           string "Location of FSP headers"
  18           default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
  19
  20 config MAX_SOCKET
  21         int
  22         default 2
  23
  24 # For 2S config, the number of cpus could be as high as
  25 # 2 threads * 20 cores * 2 sockets
  26 config MAX_CPUS
  27         int
  28         default 80
  29
  30 config CPU_BCLK_MHZ
  31         int
  32         default 100
  33
  34 config PCR_BASE_ADDRESS
  35         hex
  36         default 0xfd000000
  37         help
  38           This option allows you to select MMIO Base Address of sideband bus.
  39
  40 config DCACHE_RAM_BASE
  41         hex
  42         default 0xfe800000
  43
  44 config DCACHE_RAM_SIZE
  45         hex
  46         default 0x200000
  47
  48 config DCACHE_BSP_STACK_SIZE
  49         hex
  50         default 0x10000
  51
  52 config CPU_MICROCODE_CBFS_LOC
  53         hex
  54         default 0xfff0fdc0
  55
  56 config CPU_MICROCODE_CBFS_LEN
  57         hex
  58         default 0x7C00
  59
  60 config IED_REGION_SIZE
  61         hex
  62         default 0x400000
  63
  64 config IFD_CHIPSET
  65         string
  66         default "lbg"
  67
  68 endif