src/soc/intel/xeon_sp/skx/Makefile.mk

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y)
   4
   5 subdirs-y += ../../../../cpu/intel/microcode
   6 subdirs-y += ../../../../cpu/intel/turbo
   7
   8 postcar-y += soc_util.c
   9
  10 romstage-y += soc_util.c
  11 romstage-y += romstage.c
  12 romstage-y += soc_util.c
  13 romstage-y += hob_display.c
  14 romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
  15 romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
  16
  17 ramstage-y += soc_acpi.c
  18 ramstage-y += chip.c
  19 ramstage-y += ../chip_gen1.c ../lpc_gen1.c
  20 ramstage-y += soc_util.c
  21 ramstage-y += cpu.c
  22 ramstage-y += ioapic.c
  23 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
  24 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
  25 ramstage-y += hob_display.c
  26 ramstage-y += ../pcu0.c
  27 ramstage-y += ../pcu1.c
  28 ramstage-y += ../pcu2.c
  29 ramstage-y += ../pcu3.c
  30 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx
  31
  32 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04
  33
  34 endif ## CONFIG_SOC_INTEL_SKYLAKE_SP