1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #include <acpi/acpigen_pci.h>
4 #include <console/console.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
8 #include <intelblocks/acpi.h>
10 #include <soc/chip_common.h>
13 #include <soc/pci_devs.h>
14 #include <soc/soc_pch.h>
15 #include <soc/ramstage.h>
16 #include <soc/soc_util.h>
19 static struct device_operations cpu_bus_ops
= {
20 .read_resources
= noop_read_resources
,
21 .set_resources
= noop_set_resources
,
22 .init
= mp_cpu_bus_init
,
23 #if CONFIG(HAVE_ACPI_TABLES)
24 /* defined in src/soc/intel/common/block/acpi/acpi.c */
25 .acpi_fill_ssdt
= generate_cpu_entries
,
29 static void soc_enable_dev(struct device
*dev
)
31 /* Set the operations if it is a special bus type */
32 if (dev
->path
.type
== DEVICE_PATH_DOMAIN
) {
33 /* domain ops are assigned at their creation */
34 } else if (dev
->path
.type
== DEVICE_PATH_CPU_CLUSTER
) {
35 dev
->ops
= &cpu_bus_ops
;
36 } else if (dev
->path
.type
== DEVICE_PATH_GPIO
) {
37 block_gpio_enable(dev
);
41 static void set_imc_locks(void)
43 struct device
*dev
= 0;
44 while ((dev
= dev_find_device(PCI_VID_INTEL
, IMC_M2MEM_DEVID
, dev
)))
45 pci_or_config32(dev
, IMC_M2MEM_TIMEOUT
, TIMEOUT_LOCK
);
48 static void set_upi_locks(void)
50 struct device
*dev
= 0;
51 while ((dev
= dev_find_device(PCI_VID_INTEL
, UPI_LL_CR_DEVID
, dev
)))
52 pci_or_config32(dev
, UPI_LL_CR_KTIMISCMODLCK
, KTIMISCMODLCK_LOCK
);
55 static void soc_final(void *data
)
57 // Temp Fix - should be done by FSP, in 2S bios completion
58 // is not carried out on socket 2
63 static void soc_init(void *data
)
65 printk(BIOS_DEBUG
, "coreboot: calling fsp_silicon_init\n");
71 override_hpet_ioapic_bdf();
75 void platform_fsp_silicon_init_params_cb(FSPS_UPD
*silupd
)
77 mainboard_silicon_init_params(silupd
);
80 struct chip_operations soc_intel_xeon_sp_skx_ops
= {
81 .name
= "Intel Skylake-SP",
82 .enable_dev
= soc_enable_dev
,
87 struct pci_operations soc_pci_ops
= {
88 .set_subsystem
= pci_dev_set_subsystem
,