util/chromeos/crosfirmware: Improve parsing of manifest.json
[coreboot.git] / src / soc / intel / xeon_sp / skx / ioapic.c
blob99a5368ffd87a1d6e0ccbe41994f708805256936
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
6 #include <soc/acpi.h>
7 #include <soc/pci_devs.h>
8 #include <soc/ramstage.h>
9 #include <soc/chip_common.h>
11 static void ioapic_read_resources(struct device *dev)
13 pci_dev_read_resources(dev);
15 u16 abar = pci_read_config16(dev, APIC_ABAR);
16 if (!abar)
17 return;
18 const u32 addr = IO_APIC_ADDR | ((abar & 0xfff) << 8);
20 printk(BIOS_DEBUG, " %s: IOAPIC Address: 0x%x\n",
21 dev_path(dev), addr);
23 mmio_range(dev, APIC_ABAR, addr, 0x100);
26 static void ioapic_init(struct device *dev)
28 struct resource *resource;
30 pci_dev_init(dev);
32 /* See if there is a resource with the appropriate index. */
33 resource = probe_resource(dev, APIC_ABAR);
34 if (!resource)
35 return;
37 const union xeon_domain_path dn = {
38 .domain_path = dev_get_domain_id(dev)
41 /* 14nm Xeon-SP has up to 6 stacks per socket */
42 assert(dn.stack < MAX_LOGIC_IIO_STACK);
44 /* Assign socket specific GSI_BASE */
45 const u32 gsi_base = 24 + (dn.socket * MAX_LOGIC_IIO_STACK + dn.stack) * 8;
47 ioapic_create_dev(dev, resource->base, gsi_base);
50 static const unsigned short ioapic_ids[] = {
51 0x2036,
52 0x2026,
56 static struct device_operations ioapic_ops = {
57 .read_resources = ioapic_read_resources,
58 .set_resources = pci_dev_set_resources,
59 .enable_resources = pci_dev_enable_resources,
60 .init = ioapic_init,
63 static const struct pci_driver ioapic_driver __pci_driver = {
64 .ops = &ioapic_ops,
65 .vendor = PCI_VID_INTEL,
66 .devices = ioapic_ids,