src/southbridge/intel/i82801ix/pcie.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ops.h>
   7 #include <device/pciexp.h>
   8 #include <device/pci_ids.h>
   9 #include <southbridge/intel/common/pciehp.h>
  10 #include "chip.h"
  11
  12 static void pci_init(struct device *dev)
  13 {
  14         struct southbridge_intel_i82801ix_config *config = dev->chip_info;
  15
  16         printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n");
  17
  18         /* Enable Bus Master */
  19         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
  20
  21         /* Set Cache Line Size to 0x10 */
  22         // This has no effect but the OS might expect it
  23         pci_write_config8(dev, 0x0c, 0x10);
  24
  25         pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
  26
  27         /* Enable IO xAPIC on this PCIe port */
  28         pci_or_config32(dev, 0xd8, 1 << 7);
  29
  30         /* Enable Backbone Clock Gating */
  31         pci_or_config32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
  32
  33         /* Set VC0 transaction class */
  34         pci_update_config32(dev, 0x114, ~0x000000ff, 1);
  35
  36         /* Mask completion timeouts */
  37         pci_or_config32(dev, 0x148, 1 << 14);
  38
  39         /* Lock R/WO Correctable Error Mask. */
  40         pci_update_config32(dev, 0x154, ~0, 0);
  41
  42         /* Clear errors in status registers */
  43         pci_update_config16(dev, 0x06, ~0, 0);
  44         pci_update_config16(dev, 0x1e, ~0, 0);
  45
  46         /* Get configured ASPM state */
  47         const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3;
  48
  49         /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
  50         if (apmc == PCIE_ASPM_BOTH)
  51                 pci_or_config32(dev, 0xe8, 1 << 1);
  52
  53         /* Enable expresscard hotplug events.  */
  54         if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
  55                 pci_or_config32(dev, 0xd8, 1 << 30);
  56                 pci_write_config16(dev, 0x42, 0x142);
  57         }
  58 }
  59
  60 static void pch_pciexp_scan_bridge(struct device *dev)
  61 {
  62         struct southbridge_intel_i82801ix_config *config = dev->chip_info;
  63
  64         if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
  65                 pciexp_hotplug_scan_bridge(dev);
  66         } else {
  67                 /* Normal PCIe Scan */
  68                 pciexp_scan_bridge(dev);
  69         }
  70 }
  71
  72 static struct device_operations device_ops = {
  73         .read_resources         = pci_bus_read_resources,
  74         .set_resources          = pci_dev_set_resources,
  75         .enable_resources       = pci_bus_enable_resources,
  76         .init                   = pci_init,
  77         .scan_bus               = pch_pciexp_scan_bridge,
  78         .ops_pci                = &pci_dev_ops_pci,
  79 };
  80
  81 /* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */
  82 static const unsigned short pci_device_ids[] = {
  83         PCI_DID_INTEL_82801IB_PCIE1, /* Port 1 */
  84         PCI_DID_INTEL_82801IB_PCIE2, /* Port 2 */
  85         PCI_DID_INTEL_82801IB_PCIE3, /* Port 3 */
  86         PCI_DID_INTEL_82801IB_PCIE4, /* Port 4 */
  87         PCI_DID_INTEL_82801IB_PCIE5, /* Port 5 */
  88         PCI_DID_INTEL_82801IB_PCIE6, /* Port 6 */
  89         0
  90 };
  91 static const struct pci_driver ich9_pcie __pci_driver = {
  92         .ops            = &device_ops,
  93         .vendor         = PCI_VID_INTEL,
  94         .devices        = pci_device_ids,
  95 };