soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING
[coreboot.git] / src / southbridge / intel / i82801ix / thermal.c
blob543b2ffd3864be771e229cb7b84165102ffd0dae
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <device/pci_ids.h>
9 #include "i82801ix.h"
11 static void thermal_init(struct device *dev)
13 if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0)))
14 return;
16 u8 reg8;
18 pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR);
19 pci_or_config32(dev, 0x04, 1 << 1);
21 write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */
22 write32(DEFAULT_TBAR + 0x44, 0);
24 write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */
25 write8(DEFAULT_TBAR + 0x41, 0xba);
27 reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */
28 write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7));
29 reg8 = read8(DEFAULT_TBAR + 0x48);
30 write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7));
32 pci_and_config32(dev, 0x04, ~(1 << 1));
33 pci_write_config32(dev, 0x10, 0);
36 static struct device_operations device_ops = {
37 .read_resources = pci_dev_read_resources,
38 .set_resources = pci_dev_set_resources,
39 .enable_resources = pci_dev_enable_resources,
40 .init = thermal_init,
41 .ops_pci = &pci_dev_ops_pci,
44 static const struct pci_driver ich9_thermal __pci_driver = {
45 .ops = &device_ops,
46 .vendor = PCI_VID_INTEL,
47 .device = PCI_DID_INTEL_82801IB_THERMAL,