src/southbridge/intel/i82801jx/lpc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <option.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <pc80/isa-dma.h>
  10 #include <pc80/i8259.h>
  11 #include <arch/io.h>
  12 #include <device/pci_ops.h>
  13 #include <arch/ioapic.h>
  14 #include <acpi/acpi.h>
  15 #include <cpu/x86/smm.h>
  16 #include <cpu/intel/speedstep.h>
  17 #include <acpi/acpigen.h>
  18 #include <arch/smp/mpspec.h>
  19 #include "chip.h"
  20 #include "i82801jx.h"
  21 #include <southbridge/intel/common/pciehp.h>
  22 #include <southbridge/intel/common/pmutil.h>
  23 #include <southbridge/intel/common/acpi_pirq_gen.h>
  24 #include <southbridge/intel/common/rcba_pirq.h>
  25 #include <static.h>
  26
  27 #define NMI_OFF 0
  28
  29 typedef struct southbridge_intel_i82801jx_config config_t;
  30
  31 static void i82801jx_enable_apic(struct device *dev)
  32 {
  33         /* Enable IOAPIC. Keep APIC Range Select at zero. */
  34         RCBA8(0x31ff) = 0x03;
  35         /* We have to read 0x31ff back if bit0 changed. */
  36         RCBA8(0x31ff);
  37
  38         /* Lock maximum redirection entries (MRE), R/WO register. */
  39         ioapic_lock_max_vectors(IO_APIC_ADDR);
  40
  41         register_new_ioapic_gsi0(IO_APIC_ADDR);
  42 }
  43
  44 static void i82801jx_enable_serial_irqs(struct device *dev)
  45 {
  46         /* Set packet length and toggle silent mode bit for one frame. */
  47         pci_write_config8(dev, D31F0_SERIRQ_CNTL,
  48                           (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
  49 }
  50
  51 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  52  * 0x00 - 0000 = Reserved
  53  * 0x01 - 0001 = Reserved
  54  * 0x02 - 0010 = Reserved
  55  * 0x03 - 0011 = IRQ3
  56  * 0x04 - 0100 = IRQ4
  57  * 0x05 - 0101 = IRQ5
  58  * 0x06 - 0110 = IRQ6
  59  * 0x07 - 0111 = IRQ7
  60  * 0x08 - 1000 = Reserved
  61  * 0x09 - 1001 = IRQ9
  62  * 0x0A - 1010 = IRQ10
  63  * 0x0B - 1011 = IRQ11
  64  * 0x0C - 1100 = IRQ12
  65  * 0x0D - 1101 = Reserved
  66  * 0x0E - 1110 = IRQ14
  67  * 0x0F - 1111 = IRQ15
  68  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  69  * 0x80 - The PIRQ is not routed.
  70  */
  71
  72 static void i82801jx_pirq_init(struct device *dev)
  73 {
  74         struct device *irq_dev;
  75
  76         /* Interrupt 11 is not used by legacy devices and so can always be used
  77          * for PCI interrupts. Full legacy IRQ routing is complicated and hard
  78          * to get right. Fortunately all modern OS use MSI and so it's not that
  79          * big of an issue anyway. Still we have to provide a reasonable
  80          * default. Using interrupt 11 for it everywhere is a working default.
  81          * ACPI-aware OS can move it to any interrupt and others will just leave
  82          * them at default.
  83          */
  84         const u8 pirq_routing = 11;
  85
  86         pci_write_config8(dev, D31F0_PIRQA_ROUT, pirq_routing);
  87         pci_write_config8(dev, D31F0_PIRQB_ROUT, pirq_routing);
  88         pci_write_config8(dev, D31F0_PIRQC_ROUT, pirq_routing);
  89         pci_write_config8(dev, D31F0_PIRQD_ROUT, pirq_routing);
  90
  91         pci_write_config8(dev, D31F0_PIRQE_ROUT, pirq_routing);
  92         pci_write_config8(dev, D31F0_PIRQF_ROUT, pirq_routing);
  93         pci_write_config8(dev, D31F0_PIRQG_ROUT, pirq_routing);
  94         pci_write_config8(dev, D31F0_PIRQH_ROUT, pirq_routing);
  95
  96         /* Eric Biederman once said we should let the OS do this.
  97          * I am not so sure anymore he was right.
  98          */
  99
 100         for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 101                 u8 int_pin = 0;
 102
 103                 if (!is_enabled_pci(irq_dev))
 104                         continue;
 105
 106                 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
 107
 108                 if (int_pin == 0)
 109                         continue;
 110
 111                 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing);
 112         }
 113 }
 114
 115 static void i82801jx_gpi_routing(struct device *dev)
 116 {
 117         /* Get the chip configuration */
 118         config_t *config = dev->chip_info;
 119         u32 reg32 = 0;
 120
 121         /* An array would be much nicer here, or some
 122          * other method of doing this.
 123          */
 124         reg32 |= (config->gpi0_routing & 0x03) << 0;
 125         reg32 |= (config->gpi1_routing & 0x03) << 2;
 126         reg32 |= (config->gpi2_routing & 0x03) << 4;
 127         reg32 |= (config->gpi3_routing & 0x03) << 6;
 128         reg32 |= (config->gpi4_routing & 0x03) << 8;
 129         reg32 |= (config->gpi5_routing & 0x03) << 10;
 130         reg32 |= (config->gpi6_routing & 0x03) << 12;
 131         reg32 |= (config->gpi7_routing & 0x03) << 14;
 132         reg32 |= (config->gpi8_routing & 0x03) << 16;
 133         reg32 |= (config->gpi9_routing & 0x03) << 18;
 134         reg32 |= (config->gpi10_routing & 0x03) << 20;
 135         reg32 |= (config->gpi11_routing & 0x03) << 22;
 136         reg32 |= (config->gpi12_routing & 0x03) << 24;
 137         reg32 |= (config->gpi13_routing & 0x03) << 26;
 138         reg32 |= (config->gpi14_routing & 0x03) << 28;
 139         reg32 |= (config->gpi15_routing & 0x03) << 30;
 140
 141         pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
 142 }
 143
 144 bool southbridge_support_c5(void)
 145 {
 146         struct device *lpc_dev = __pci_0_1f_0;
 147         struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info;
 148         return config->c5_enable;
 149 }
 150
 151 bool southbridge_support_c6(void)
 152 {
 153         struct device *lpc_dev = __pci_0_1f_0;
 154         struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info;
 155         return config->c6_enable;
 156 }
 157
 158 static void i82801jx_power_options(struct device *dev)
 159 {
 160         u8 reg8;
 161         u16 reg16, pmbase;
 162         u32 reg32;
 163         const char *state;
 164         /* Get the chip configuration */
 165         config_t *config = dev->chip_info;
 166
 167         /* BIOS must program... */
 168         pci_or_config32(dev, 0xac, (1 << 30) | (3 << 8));
 169
 170         /* Which state do we want to goto after g3 (power restored)?
 171          * 0 == S0 Full On
 172          * 1 == S5 Soft Off
 173          *
 174          * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
 175          */
 176         const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
 177
 178         reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
 179         reg8 &= 0xfe;
 180         switch (pwr_on) {
 181         case MAINBOARD_POWER_OFF:
 182                 reg8 |= 1;
 183                 state = "off";
 184                 break;
 185         case MAINBOARD_POWER_ON:
 186                 reg8 &= ~1;
 187                 state = "on";
 188                 break;
 189         case MAINBOARD_POWER_KEEP:
 190                 reg8 &= ~1;
 191                 state = "state keep";
 192                 break;
 193         default:
 194                 state = "undefined";
 195         }
 196
 197         reg8 |= (3 << 4);       /* avoid #S4 assertions */
 198         reg8 &= ~(1 << 3);      /* minimum assertion is 1 to 2 RTCCLK */
 199
 200         pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8);
 201         printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 202
 203         /* Set up NMI on errors. */
 204         reg8 = inb(0x61);
 205         reg8 &= 0x0f;           /* Higher Nibble must be 0 */
 206         reg8 &= ~(1 << 3);      /* IOCHK# NMI Enable */
 207         // reg8 &= ~(1 << 2);   /* PCI SERR# Enable */
 208         reg8 |= (1 << 2); /* PCI SERR# Disable for now */
 209         outb(reg8, 0x61);
 210
 211         reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */
 212         const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
 213         if (nmi_option) {
 214                 printk(BIOS_INFO, "NMI sources enabled.\n");
 215                 reg8 &= ~(1 << 7);      /* Set NMI. */
 216         } else {
 217                 printk(BIOS_INFO, "NMI sources disabled.\n");
 218                 reg8 |= (1 << 7);       /* Can't mask NMI from PCI-E and NMI_NOW */
 219         }
 220         outb(reg8, 0x70);
 221
 222         /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
 223         reg16 = pci_read_config16(dev, D31F0_GEN_PMCON_1);
 224         reg16 &= ~(3 << 0);     // SMI# rate 1 minute
 225         reg16 |= (1 << 2);      // CLKRUN_EN - Mobile/Ultra only
 226         reg16 |= (1 << 3);      // Speedstep Enable - Mobile/Ultra only
 227         reg16 |= (1 << 5);      // CPUSLP_EN Desktop only
 228
 229         if (config->c4onc3_enable)
 230                 reg16 |= (1 << 7);
 231
 232         // another laptop wants this?
 233         // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
 234         reg16 |= (1 << 10);     // BIOS_PCI_EXP_EN - Desktop/Mobile only
 235         if (CONFIG(DEBUG_PERIODIC_SMI))
 236                 reg16 |= (3 << 0); // Periodic SMI every 8s
 237         if (southbridge_support_c5())
 238                 reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */
 239         pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16);
 240
 241         /* Set exit timings for C5/C6. */
 242         if (southbridge_support_c5()) {
 243                 reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING);
 244                 reg8 &= ~((7 << 3) | (7 << 0));
 245                 if (southbridge_support_c6())
 246                         reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#,
 247                                                         95-102us DPRSTP# to STP_CPU# */
 248                 else
 249                         reg8 |= (0 << 3) | (1 << 0); /* 16-17us PMSYNC# to STPCLK#,
 250                                                         34-40us DPRSTP# to STP_CPU# */
 251                 pci_write_config8(dev, D31F0_C5_EXIT_TIMING, reg8);
 252         }
 253
 254         // Set the board's GPI routing.
 255         i82801jx_gpi_routing(dev);
 256
 257         pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
 258
 259         outl(config->gpe0_en, pmbase + 0x28);
 260         outw(config->alt_gp_smi_en, pmbase + 0x38);
 261
 262         /* Set up power management block and determine sleep mode */
 263         reg16 = inw(pmbase + 0x00); /* PM1_STS */
 264         outw(reg16, pmbase + 0x00); /* Clear status bits. At least bit11 (power
 265                                        button override) must be cleared or SCI
 266                                        will be constantly fired and OSPM must
 267                                        not know about it (ACPI spec says to
 268                                        ignore the bit). */
 269         reg32 = inl(pmbase + 0x04); // PM1_CNT
 270         reg32 &= ~(7 << 10);    // SLP_TYP
 271         outl(reg32, pmbase + 0x04);
 272
 273         /* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */
 274         reg32 = inl(pmbase + 0x10);
 275         reg32 &= ~(7 << 5);
 276         reg32 |= (config->throttle_duty & 7) << 5;
 277         outl(reg32, pmbase + 0x10);
 278 }
 279
 280 static void i82801jx_rtc_init(struct device *dev)
 281 {
 282         u8 reg8;
 283         int rtc_failed;
 284
 285         reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
 286         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 287         if (rtc_failed) {
 288                 reg8 &= ~RTC_BATTERY_DEAD;
 289                 pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8);
 290         }
 291         printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 292
 293         cmos_init(rtc_failed);
 294 }
 295
 296 static void enable_hpet(void)
 297 {
 298         u32 reg32;
 299
 300         /* Move HPET to default address 0xfed00000 and enable it */
 301         reg32 = RCBA32(RCBA_HPTC);
 302         reg32 |= (1 << 7); // HPET Address Enable
 303         reg32 &= ~(3 << 0);
 304         RCBA32(RCBA_HPTC) = reg32;
 305 }
 306
 307 static void enable_clock_gating(void)
 308 {
 309         u32 reg32;
 310
 311         /* Enable DMI dynamic clock gating. */
 312         RCBA32(RCBA_DMIC) |= 3;
 313
 314         /* Enable Clock Gating for most devices. */
 315         reg32 = RCBA32(RCBA_CG);
 316         reg32 |= (1 << 31);     /* LPC dynamic clock gating */
 317         /* USB UHCI dynamic clock gating: */
 318         reg32 |= (1 << 29) | (1 << 28);
 319         /* SATA dynamic clock gating [0-3]: */
 320         reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
 321         reg32 |= (1 << 23);     /* LAN static clock gating (if LAN disabled) */
 322         reg32 |= (1 << 22);     /* HD audio dynamic clock gating */
 323         reg32 &= ~(1 << 21);    /* No HD audio static clock gating */
 324         reg32 &= ~(1 << 20);    /* No USB EHCI static clock gating */
 325         reg32 |= (1 << 19);     /* USB EHCI dynamic clock gating */
 326         /* More SATA dynamic clock gating [4-5]: */
 327         reg32 |= (1 << 18) | (1 << 17);
 328         reg32 |= (1 << 16);     /* PCI dynamic clock gating */
 329         /* PCIe, DMI dynamic clock gating: */
 330         reg32 |= (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1);
 331         reg32 |= (1 << 0);      /* PCIe root port static clock gating */
 332         RCBA32(RCBA_CG) = reg32;
 333
 334         /* Enable SPI dynamic clock gating. */
 335         RCBA32(0x38c0) |= 7;
 336 }
 337
 338 static void i82801jx_set_acpi_mode(struct device *dev)
 339 {
 340         if (!acpi_is_wakeup_s3()) {
 341                 apm_control(APM_CNT_ACPI_DISABLE);
 342         } else {
 343                 apm_control(APM_CNT_ACPI_ENABLE);
 344         }
 345 }
 346
 347 static void lpc_init(struct device *dev)
 348 {
 349         printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
 350
 351         /* IO APIC initialization. */
 352         i82801jx_enable_apic(dev);
 353
 354         i82801jx_enable_serial_irqs(dev);
 355
 356         /* Setup the PIRQ. */
 357         i82801jx_pirq_init(dev);
 358
 359         /* Setup power options. */
 360         i82801jx_power_options(dev);
 361
 362         /* Initialize the real time clock. */
 363         i82801jx_rtc_init(dev);
 364
 365         /* Initialize ISA DMA. */
 366         isa_dma_init();
 367
 368         /* Initialize the High Precision Event Timers, if present. */
 369         enable_hpet();
 370
 371         /* Initialize Clock Gating */
 372         enable_clock_gating();
 373
 374         setup_i8259();
 375
 376         /* The OS should do this? */
 377         /* Interrupt 9 should be level triggered (SCI) */
 378         i8259_configure_irq_trigger(9, 1);
 379
 380         i82801jx_set_acpi_mode(dev);
 381 }
 382
 383 static void i82801jx_lpc_read_resources(struct device *dev)
 384 {
 385         int i, io_index = 0;
 386         /*
 387          *             I/O Resources
 388          *
 389          * 0x0000 - 0x000f....ISA DMA
 390          * 0x0010 - 0x001f....ISA DMA aliases
 391          * 0x0020 ~ 0x003d....PIC
 392          * 0x002e - 0x002f....Maybe Super I/O
 393          * 0x0040 - 0x0043....Timer
 394          * 0x004e - 0x004f....Maybe Super I/O
 395          * 0x0050 - 0x0053....Timer aliases
 396          * 0x0061.............NMI_SC
 397          * 0x0070.............NMI_EN (readable in alternative access mode)
 398          * 0x0070 - 0x0077....RTC
 399          * 0x0080 - 0x008f....ISA DMA
 400          * 0x0090 ~ 0x009f....ISA DMA aliases
 401          * 0x0092.............Fast A20 and Init
 402          * 0x00a0 ~ 0x00bd....PIC
 403          * 0x00b2 - 0x00b3....APM
 404          * 0x00c0 ~ 0x00de....ISA DMA
 405          * 0x00c1 ~ 0x00df....ISA DMA aliases
 406          * 0x00f0.............Coprocessor Error
 407          * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit)
 408          * 0x04d0 - 0x04d1....PIC
 409          * 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
 410          * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)
 411          * 0x05c0 - 0x05ff....SB GPIO cont. (mobile only)
 412          * 0x0cf8 - 0x0cff....PCI
 413          * 0x0cf9.............Reset Control
 414          */
 415
 416         struct resource *res;
 417
 418         /* Get the normal PCI resources of this device. */
 419         pci_dev_read_resources(dev);
 420
 421         /* Add an extra subtractive resource for both memory and I/O. */
 422         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 423         res->base = 0;
 424         res->size = 0x1000;
 425         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 426                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 427
 428         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 429         res->base = 0xff000000;
 430         res->size = 0x01000000; /* 16 MB for flash */
 431         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 432                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 433
 434         res = new_resource(dev, 3); /* IOAPIC */
 435         res->base = IO_APIC_ADDR;
 436         res->size = 0x00001000;
 437         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 438
 439         /* Set IO decode ranges if required.*/
 440         for (i = 0; i < 4; i++) {
 441                 u32 gen_dec;
 442                 gen_dec = pci_read_config32(dev, 0x84 + 4 * i);
 443
 444                 if ((gen_dec & 0xFFFC) > 0x1000) {
 445                         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 446                         res->base = gen_dec & 0xFFFC;
 447                         res->size = (gen_dec >> 16) & 0xFC;
 448                         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 449                                 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 450                 }
 451         }
 452 }
 453
 454 static const char *lpc_acpi_name(const struct device *dev)
 455 {
 456         return "LPCB";
 457 }
 458
 459 static void southbridge_fill_ssdt(const struct device *device)
 460 {
 461         struct device *dev = pcidev_on_root(0x1f, 0);
 462         config_t *chip = dev->chip_info;
 463
 464         intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
 465         intel_acpi_gen_def_acpi_pirq(device);
 466 }
 467
 468 static struct device_operations device_ops = {
 469         .read_resources         = i82801jx_lpc_read_resources,
 470         .set_resources          = pci_dev_set_resources,
 471         .enable_resources       = pci_dev_enable_resources,
 472         .write_acpi_tables      = acpi_write_hpet,
 473         .acpi_fill_ssdt         = southbridge_fill_ssdt,
 474         .acpi_name              = lpc_acpi_name,
 475         .init                   = lpc_init,
 476         .scan_bus               = scan_static_bus,
 477         .ops_pci                = &pci_dev_ops_pci,
 478 };
 479
 480 static const unsigned short pci_device_ids[] = {
 481         0x3a10, /* ICH10R Eng. Sample */
 482         0x3a14, /* ICH10DO */
 483         0x3a16, /* ICH10R */
 484         0x3a18, /* ICH10 */
 485         0x3a1a, /* ICH10D */
 486         0x3a1e, /* ICH10 Eng. Sample */
 487         0
 488 };
 489
 490 static const struct pci_driver ich10_lpc __pci_driver = {
 491         .ops            = &device_ops,
 492         .vendor         = PCI_VID_INTEL,
 493         .devices        = pci_device_ids,
 494 };