MAINTAINERS: Add Yuchi and Vasiliy for Intel Atom Snow Ridge SoC
[coreboot.git] / src / southbridge / intel / lynxpoint / fadt.c
blob2eec269ee046f7ad72f6c61ce6aa97bf9c719280
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/pci_ops.h>
4 #include <acpi/acpi.h>
5 #include <southbridge/intel/lynxpoint/pch.h>
6 #include "chip.h"
8 void acpi_fill_fadt(acpi_fadt_t *fadt)
10 struct device *dev = pcidev_on_root(0x1f, 0);
11 struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info;
12 u16 pmbase = get_pmbase();
15 fadt->pm1a_evt_blk = pmbase + PM1_STS;
16 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
17 fadt->pm2_cnt_blk = pmbase + PM2_CNT;
18 fadt->pm_tmr_blk = pmbase + PM1_TMR;
19 if (pch_is_lp())
20 fadt->gpe0_blk = pmbase + LP_GPE0_STS_1;
21 else
22 fadt->gpe0_blk = pmbase + GPE0_STS;
25 * Some of the lengths here are doubled. This is because they describe
26 * blocks containing two registers, where the size of each register
27 * is found by halving the block length. See Table 5-34 and section
28 * 4.8.3 of the ACPI specification for details.
30 fadt->pm1_evt_len = 2 * 2;
31 fadt->pm1_cnt_len = 2;
32 fadt->pm2_cnt_len = 1;
33 fadt->pm_tmr_len = 4;
34 if (pch_is_lp())
35 fadt->gpe0_blk_len = 2 * 16;
36 else
37 fadt->gpe0_blk_len = 2 * 8;
39 fill_fadt_extended_pm_io(fadt);
41 fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
43 fadt->flags |= ACPI_FADT_WBINVD |
44 ACPI_FADT_C1_SUPPORTED |
45 ACPI_FADT_SLEEP_BUTTON |
46 ACPI_FADT_SEALED_CASE |
47 ACPI_FADT_S4_RTC_WAKE |
48 ACPI_FADT_PLATFORM_CLOCK;
50 if (cfg && cfg->docking_supported)
51 fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;