src/southbridge/intel/lynxpoint/pcie.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <commonlib/helpers.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pciexp.h>
   9 #include <device/pci_ids.h>
  10 #include <device/pci_ops.h>
  11 #include "iobp.h"
  12 #include "pch.h"
  13 #include <southbridge/intel/common/gpio.h>
  14 #include <stdint.h>
  15 #include "chip.h"
  16
  17 #define MAX_NUM_ROOT_PORTS 8
  18
  19 struct root_port_config {
  20         /* RPFN is a write-once register so keep a copy until it is written */
  21         u32 orig_rpfn;
  22         u32 new_rpfn;
  23         u32 pin_ownership;
  24         u32 strpfusecfg1;
  25         u32 strpfusecfg2;
  26         u32 strpfusecfg3;
  27         u32 b0d28f0_32c;
  28         u32 b0d28f4_32c;
  29         u32 b0d28f5_32c;
  30         bool coalesce;
  31         int gbe_port;
  32         int num_ports;
  33         struct device *ports[MAX_NUM_ROOT_PORTS];
  34 };
  35
  36 static struct root_port_config rpc;
  37
  38 static inline int max_root_ports(void)
  39 {
  40         if (pch_is_lp() || pch_silicon_id() == PCI_DID_INTEL_LPT_H81)
  41                 return 6;
  42
  43         return 8;
  44 }
  45
  46 static inline int root_port_is_first(struct device *dev)
  47 {
  48         return PCI_FUNC(dev->path.pci.devfn) == 0;
  49 }
  50
  51 static inline int root_port_is_last(struct device *dev)
  52 {
  53         return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
  54 }
  55
  56 /* Root ports are numbered 1..N in the documentation. */
  57 static inline int root_port_number(struct device *dev)
  58 {
  59         return PCI_FUNC(dev->path.pci.devfn) + 1;
  60 }
  61
  62 static bool is_rp_enabled(int rp)
  63 {
  64         ASSERT(rp > 0 && rp <= ARRAY_SIZE(rpc.ports));
  65
  66         if (rpc.ports[rp - 1] == NULL)
  67                 return false;
  68
  69         return rpc.ports[rp - 1]->enabled;
  70 }
  71
  72 static void root_port_config_update_gbe_port(void)
  73 {
  74         /* Is the Gbe Port enabled? */
  75         if (!((rpc.strpfusecfg1 >> 19) & 1))
  76                 return;
  77
  78         if (pch_is_lp()) {
  79                 switch ((rpc.strpfusecfg1 >> 16) & 0x7) {
  80                 case 0:
  81                         rpc.gbe_port = 3;
  82                         break;
  83                 case 1:
  84                         rpc.gbe_port = 4;
  85                         break;
  86                 case 2:
  87                 case 3:
  88                 case 4:
  89                 case 5:
  90                         /* Lanes 0-4 of Root Port 5. */
  91                         rpc.gbe_port = 5;
  92                         break;
  93                 default:
  94                         printk(BIOS_DEBUG, "Invalid GbE Port Selection.\n");
  95                 }
  96         } else {
  97                 /* Non-LP has 1:1 mapping with root ports. */
  98                 rpc.gbe_port = ((rpc.strpfusecfg1 >> 16) & 0x7) + 1;
  99         }
 100 }
 101
 102 static void update_num_ports(void)
 103 {
 104         /*
 105          * According to existing code in 'root_port_check_disable()', which does
 106          * not agree with the confusing information on the datasheets, the last
 107          * visible function depends on the strapped root port width as follows:
 108          *
 109          * +-----+----+----+----+----+
 110          * | RPC | #5 | #6 | #7 | #8 |
 111          * +-----+----+----+----+----+
 112          * |  0  | x1 | x1 | x1 | x1 |
 113          * |  1  | x2 |    | x1 | x1 |
 114          * |  2  | x2 |    | x2 |    |
 115          * |  3  | x4 |    |    |    |
 116          * +-----+----+----+----+----+
 117          */
 118         switch ((rpc.strpfusecfg2 >> 14) & 0x3) {
 119         case 0:
 120         case 1:
 121                 break;
 122         case 2:
 123                 rpc.num_ports = MIN(rpc.num_ports, 7);
 124                 break;
 125         case 3:
 126                 rpc.num_ports = MIN(rpc.num_ports, 5);
 127                 break;
 128         }
 129
 130         printk(BIOS_DEBUG, "Adjusted number of PCIe root ports to %d as per strpfusecfg2\n",
 131                rpc.num_ports);
 132 }
 133
 134 static void root_port_init_config(struct device *dev)
 135 {
 136         int rp;
 137
 138         if (root_port_is_first(dev)) {
 139                 rpc.orig_rpfn = RCBA32(RPFN);
 140                 rpc.new_rpfn = rpc.orig_rpfn;
 141                 rpc.num_ports = max_root_ports();
 142                 rpc.gbe_port = -1;
 143
 144                 rpc.pin_ownership = pci_read_config32(dev, 0x410);
 145                 root_port_config_update_gbe_port();
 146
 147                 if (dev->chip_info != NULL) {
 148                         struct southbridge_intel_lynxpoint_config *config;
 149
 150                         config = dev->chip_info;
 151                         rpc.coalesce = config->pcie_port_coalesce;
 152                 }
 153         }
 154
 155         rp = root_port_number(dev);
 156         if (rp > rpc.num_ports) {
 157                 printk(BIOS_ERR, "Found Root Port %d, expecting %d\n",
 158                        rp, rpc.num_ports);
 159                 return;
 160         }
 161
 162         /* Read the fuse configuration and pin ownership. */
 163         switch (rp) {
 164         case 1:
 165                 rpc.strpfusecfg1 = pci_read_config32(dev, 0xfc);
 166                 rpc.b0d28f0_32c = pci_read_config32(dev, 0x32c);
 167                 break;
 168         case 5:
 169                 rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc);
 170                 rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c);
 171
 172                 if (!pch_is_lp())
 173                         update_num_ports();
 174
 175                 break;
 176         case 6:
 177                 rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c);
 178                 rpc.strpfusecfg3 = pci_read_config32(dev, 0xfc);
 179                 break;
 180         default:
 181                 break;
 182         }
 183
 184         /* Cache pci device. */
 185         rpc.ports[rp - 1] = dev;
 186 }
 187
 188 /* Update devicetree with new Root Port function number assignment */
 189 static void pch_pcie_device_set_func(int index, int pci_func)
 190 {
 191         struct device *dev;
 192         unsigned int new_devfn;
 193
 194         dev = rpc.ports[index];
 195
 196         /* Set the new PCI function field for this Root Port. */
 197         rpc.new_rpfn &= ~RPFN_FNMASK(index);
 198         rpc.new_rpfn |= RPFN_FNSET(index, pci_func);
 199
 200         /* Determine the new devfn for this port */
 201         new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, pci_func);
 202
 203         if (dev && dev->path.pci.devfn != new_devfn) {
 204                 printk(BIOS_DEBUG,
 205                        "PCH: PCIe map %02x.%1x -> %02x.%1x\n",
 206                        PCI_SLOT(dev->path.pci.devfn),
 207                        PCI_FUNC(dev->path.pci.devfn),
 208                        PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
 209
 210                 dev->path.pci.devfn = new_devfn;
 211         }
 212 }
 213
 214 static void pcie_enable_clock_gating(void)
 215 {
 216         int i;
 217         int is_lp;
 218         int enabled_ports;
 219
 220         is_lp = pch_is_lp();
 221         enabled_ports = 0;
 222
 223         for (i = 0; i < rpc.num_ports; i++) {
 224                 struct device *dev;
 225                 int rp;
 226
 227                 dev = rpc.ports[i];
 228                 if (!dev)
 229                         continue;
 230
 231                 rp = root_port_number(dev);
 232
 233                 if (!is_rp_enabled(rp)) {
 234                         /* Configure shared resource clock gating. */
 235                         if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
 236                                 pci_or_config8(dev, 0xe1, 0x3c);
 237
 238                         if (!is_lp) {
 239                                 if (rp == 1 && !is_rp_enabled(2) &&
 240                                     !is_rp_enabled(3) && !is_rp_enabled(4)) {
 241                                         pci_or_config8(dev, 0xe2, 1);
 242                                         pci_or_config8(dev, 0xe1, 1 << 7);
 243                                 }
 244                                 if (rp == 5 && !is_rp_enabled(6) &&
 245                                     !is_rp_enabled(7) && !is_rp_enabled(8)) {
 246                                         pci_or_config8(dev, 0xe2, 1);
 247                                         pci_or_config8(dev, 0xe1, 1 << 7);
 248                                 }
 249                                 continue;
 250                         }
 251
 252                         pci_or_config8(dev, 0xe2, 3 << 4);
 253                         pci_or_config32(dev, 0x420, 1 << 31);
 254
 255                         /* Per-Port CLKREQ# handling. */
 256                         if (is_lp && gpio_is_native(18 + rp - 1))
 257                                 pci_or_config32(dev, 0x420, 3 << 29);
 258
 259                         /* Enable static clock gating. */
 260                         if (rp == 1 && !is_rp_enabled(2) &&
 261                             !is_rp_enabled(3) && !is_rp_enabled(4)) {
 262                                 pci_or_config8(dev, 0xe2, 1);
 263                                 pci_or_config8(dev, 0xe1, 1 << 7);
 264                         } else if (rp == 5 || rp == 6) {
 265                                 pci_or_config8(dev, 0xe2, 1);
 266                                 pci_or_config8(dev, 0xe1, 1 << 7);
 267                         }
 268                         continue;
 269                 }
 270
 271                 enabled_ports++;
 272
 273                 /* Enable dynamic clock gating. */
 274                 pci_or_config8(dev, 0xe1, 0x03);
 275
 276                 if (is_lp) {
 277                         pci_or_config8(dev, 0xe2, 1 << 6);
 278                         pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2));
 279                 }
 280
 281                 /* Update PECR1 register. */
 282                 pci_or_config8(dev, 0xe8, 1);
 283
 284                 pci_or_config8(dev, 0x324, 1 << 5);
 285
 286                 /* Per-Port CLKREQ# handling. */
 287                 if (is_lp && gpio_is_native(18 + rp - 1))
 288                         pci_or_config32(dev, 0x420, 3 << 29);
 289
 290                 /* Configure shared resource clock gating. */
 291                 if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
 292                         pci_or_config8(dev, 0xe1, 0x3c);
 293         }
 294
 295         if (!enabled_ports && is_lp && rpc.ports[0])
 296                 pci_or_config8(rpc.ports[0], 0xe1, 1 << 6);
 297 }
 298
 299 static void root_port_commit_config(void)
 300 {
 301         int i;
 302
 303         /* If the first root port is disabled the coalesce ports. */
 304         if (!is_rp_enabled(1))
 305                 rpc.coalesce = true;
 306
 307         /* Perform clock gating configuration. */
 308         pcie_enable_clock_gating();
 309
 310         for (i = 0; i < rpc.num_ports; i++) {
 311                 struct device *dev;
 312
 313                 dev = rpc.ports[i];
 314
 315                 if (dev == NULL) {
 316                         printk(BIOS_ERR, "Root Port %d device is NULL?\n", i+1);
 317                         continue;
 318                 }
 319
 320                 if (dev->enabled)
 321                         continue;
 322
 323                 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
 324
 325                 /* Ensure memory, io, and bus master are all disabled */
 326                 pci_and_config16(dev, PCI_COMMAND,
 327                                 ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 328
 329                 /* Disable this device if possible */
 330                 pch_disable_devfn(dev);
 331         }
 332
 333         if (rpc.coalesce) {
 334                 int current_func;
 335
 336                 /* For all Root Ports N enabled ports get assigned the lower
 337                  * PCI function number. The disabled ones get upper PCI
 338                  * function numbers. */
 339                 current_func = 0;
 340                 for (i = 0; i < rpc.num_ports; i++) {
 341                         if (!is_rp_enabled(i + 1))
 342                                 continue;
 343                         pch_pcie_device_set_func(i, current_func);
 344                         current_func++;
 345                 }
 346
 347                 /* Allocate the disabled devices' PCI function number. */
 348                 for (i = 0; i < rpc.num_ports; i++) {
 349                         if (is_rp_enabled(i + 1))
 350                                 continue;
 351                         pch_pcie_device_set_func(i, current_func);
 352                         current_func++;
 353                 }
 354         }
 355
 356         printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
 357                rpc.orig_rpfn, rpc.new_rpfn);
 358         RCBA32(RPFN) = rpc.new_rpfn;
 359 }
 360
 361 static void root_port_mark_disable(struct device *dev)
 362 {
 363         /* Mark device as disabled. */
 364         dev->enabled = 0;
 365         /* Mark device to be hidden. */
 366         rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
 367 }
 368
 369 static void root_port_check_disable(struct device *dev)
 370 {
 371         int rp;
 372         int is_lp;
 373
 374         /* Device already disabled. */
 375         if (!dev->enabled) {
 376                 root_port_mark_disable(dev);
 377                 return;
 378         }
 379
 380         rp = root_port_number(dev);
 381
 382         /* Is the GbE port mapped to this Root Port? */
 383         if (rp == rpc.gbe_port) {
 384                 root_port_mark_disable(dev);
 385                 return;
 386         }
 387
 388         is_lp = pch_is_lp();
 389
 390         /* Check Root Port Configuration. */
 391         switch (rp) {
 392                 case 2:
 393                         /* Root Port 2 is disabled for all lane configurations
 394                          * but config 00b (4x1 links). */
 395                         if ((rpc.strpfusecfg1 >> 14) & 0x3) {
 396                                 root_port_mark_disable(dev);
 397                                 return;
 398                         }
 399                         break;
 400                 case 3:
 401                         /* Root Port 3 is disabled in config 11b (1x4 links). */
 402                         if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) {
 403                                 root_port_mark_disable(dev);
 404                                 return;
 405                         }
 406                         break;
 407                 case 4:
 408                         /* Root Port 4 is disabled in configs 11b (1x4 links)
 409                          * and 10b (2x2 links). */
 410                         if ((rpc.strpfusecfg1 >> 14) & 0x2) {
 411                                 root_port_mark_disable(dev);
 412                                 return;
 413                         }
 414                         break;
 415                 case 6:
 416                         if (is_lp)
 417                                 break;
 418                         /* Root Port 6 is disabled for all lane configurations
 419                          * but config 00b (4x1 links). */
 420                         if ((rpc.strpfusecfg2 >> 14) & 0x3) {
 421                                 root_port_mark_disable(dev);
 422                                 return;
 423                         }
 424                         break;
 425                 case 7:
 426                         if (is_lp)
 427                                 break;
 428                         /* Root Port 7 is disabled in config 11b (1x4 links). */
 429                         if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) {
 430                                 root_port_mark_disable(dev);
 431                                 return;
 432                         }
 433                         break;
 434                 case 8:
 435                         if (is_lp)
 436                                 break;
 437                         /* Root Port 8 is disabled in configs 11b (1x4 links)
 438                          * and 10b (2x2 links). */
 439                         if ((rpc.strpfusecfg2 >> 14) & 0x2) {
 440                                 root_port_mark_disable(dev);
 441                                 return;
 442                         }
 443                         break;
 444         }
 445
 446         /* Check Pin Ownership. */
 447         if (is_lp) {
 448                 switch (rp) {
 449                 case 1:
 450                         /* Bit 0 is Root Port 1 ownership. */
 451                         if ((rpc.pin_ownership & 0x1) == 0) {
 452                                 root_port_mark_disable(dev);
 453                                 return;
 454                         }
 455                         break;
 456                 case 2:
 457                         /* Bit 2 is Root Port 2 ownership. */
 458                         if ((rpc.pin_ownership & 0x4) == 0) {
 459                                 root_port_mark_disable(dev);
 460                                 return;
 461                         }
 462                         break;
 463                 case 6:
 464                         /* Bits 7:4 are Root Port 6 pin-lane ownership. */
 465                         if ((rpc.pin_ownership & 0xf0) == 0) {
 466                                 root_port_mark_disable(dev);
 467                                 return;
 468                         }
 469                         break;
 470                 }
 471         } else {
 472                 switch (rp) {
 473                 case 1:
 474                         /* Bits 4 and 0 are Root Port 1 ownership. */
 475                         if ((rpc.pin_ownership & 0x11) == 0) {
 476                                 root_port_mark_disable(dev);
 477                                 return;
 478                         }
 479                         break;
 480                 case 2:
 481                         /* Bits 5 and 2 are Root Port 2 ownership. */
 482                         if ((rpc.pin_ownership & 0x24) == 0) {
 483                                 root_port_mark_disable(dev);
 484                                 return;
 485                         }
 486                         break;
 487                 }
 488         }
 489 }
 490
 491 static void pcie_add_0x0202000_iobp(u32 reg)
 492 {
 493         u32 reg32;
 494
 495         reg32 = pch_iobp_read(reg);
 496         reg32 += (0x2 << 16) | (0x2 << 8);
 497         pch_iobp_write(reg, reg32);
 498 }
 499
 500 static void pch_pcie_early(struct device *dev)
 501 {
 502         struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 503         int do_aspm = 0;
 504         int rp = root_port_number(dev);
 505         int is_lp = pch_is_lp();
 506
 507         if (is_lp) {
 508                 switch (rp) {
 509                 case 1:
 510                 case 2:
 511                 case 3:
 512                 case 4:
 513                         /*
 514                          * Bits 31:28 of b0d28f0 0x32c register correspond to
 515                          * Root Ports 4:1.
 516                          */
 517                         do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
 518                         break;
 519                 case 5:
 520                         /*
 521                          * Bit 28 of b0d28f4 0x32c register corresponds to
 522                          * Root Port 5.
 523                          */
 524                         do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
 525                         break;
 526                 case 6:
 527                         /*
 528                          * Bit 29 of b0d28f5 0x32c register corresponds to
 529                          * Root Port 6.
 530                          */
 531                         do_aspm = !!(rpc.b0d28f5_32c & (1 << 29));
 532                         break;
 533                 }
 534         } else {
 535                 switch (rp) {
 536                 case 1:
 537                 case 2:
 538                 case 3:
 539                 case 4:
 540                         /*
 541                          * Bits 31:28 of b0d28f0 0x32c register correspond to
 542                          * Root Ports 4:1.
 543                          */
 544                         do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
 545                         break;
 546                 case 5:
 547                 case 6:
 548                 case 7:
 549                 case 8:
 550                         /*
 551                          * Bits 31:28 of b0d28f4 0x32c register correspond to
 552                          * Root Ports 8:5.
 553                          */
 554                         do_aspm = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5)));
 555                         break;
 556                 }
 557         }
 558
 559         /* Allow ASPM to be forced on in devicetree */
 560         if (config && (config->pcie_port_force_aspm & (1 << (rp - 1))))
 561                 do_aspm = 1;
 562
 563         printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n",
 564                rp, do_aspm ? "en" : "dis");
 565
 566         if (do_aspm) {
 567                 /* Set ASPM bits in MPC2 register. */
 568                 pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
 569
 570                 /* Set unique clock exit latency in MPC register. */
 571                 pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
 572
 573                 if (is_lp) {
 574                         switch (rp) {
 575                         case 1:
 576                                 pcie_add_0x0202000_iobp(0xe9002440);
 577                                 break;
 578                         case 2:
 579                                 pcie_add_0x0202000_iobp(0xe9002640);
 580                                 break;
 581                         case 3:
 582                                 pcie_add_0x0202000_iobp(0xe9000840);
 583                                 break;
 584                         case 4:
 585                                 pcie_add_0x0202000_iobp(0xe9000a40);
 586                                 break;
 587                         case 5:
 588                                 pcie_add_0x0202000_iobp(0xe9000c40);
 589                                 pcie_add_0x0202000_iobp(0xe9000e40);
 590                                 pcie_add_0x0202000_iobp(0xe9001040);
 591                                 pcie_add_0x0202000_iobp(0xe9001240);
 592                                 break;
 593                         case 6:
 594                                 /* Update IOBP based on lane ownership. */
 595                                 if (rpc.pin_ownership & (1 << 4))
 596                                         pcie_add_0x0202000_iobp(0xea002040);
 597                                 if (rpc.pin_ownership & (1 << 5))
 598                                         pcie_add_0x0202000_iobp(0xea002240);
 599                                 if (rpc.pin_ownership & (1 << 6))
 600                                         pcie_add_0x0202000_iobp(0xea002440);
 601                                 if (rpc.pin_ownership & (1 << 7))
 602                                         pcie_add_0x0202000_iobp(0xea002640);
 603                                 break;
 604                         }
 605                 } else {
 606                         switch (rp) {
 607                         case 1:
 608                                 if ((rpc.pin_ownership & 0x3) == 1)
 609                                         pcie_add_0x0202000_iobp(0xe9002e40);
 610                                 else
 611                                         pcie_add_0x0202000_iobp(0xea002040);
 612                                 break;
 613                         case 2:
 614                                 if ((rpc.pin_ownership & 0xc) == 0x4)
 615                                         pcie_add_0x0202000_iobp(0xe9002c40);
 616                                 else
 617                                         pcie_add_0x0202000_iobp(0xea002240);
 618                                 break;
 619                         case 3:
 620                                 pcie_add_0x0202000_iobp(0xe9002a40);
 621                                 break;
 622                         case 4:
 623                                 pcie_add_0x0202000_iobp(0xe9002840);
 624                                 break;
 625                         case 5:
 626                                 pcie_add_0x0202000_iobp(0xe9002640);
 627                                 break;
 628                         case 6:
 629                                 pcie_add_0x0202000_iobp(0xe9002440);
 630                                 break;
 631                         case 7:
 632                                 pcie_add_0x0202000_iobp(0xe9002240);
 633                                 break;
 634                         case 8:
 635                                 pcie_add_0x0202000_iobp(0xe9002040);
 636                                 break;
 637                         }
 638                 }
 639
 640                 pci_and_config32(dev, 0x338, ~(1 << 26));
 641         }
 642
 643         /* Enable LTR in Root Port. Disable OBFF. */
 644         pci_update_config32(dev, 0x64, ~(3 << 18), 1 << 11);
 645         pci_update_config16(dev, 0x68, ~(3 << 13), 1 << 10);
 646
 647         pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
 648
 649         /* Set L1 exit latency in LCAP register. */
 650         if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm)
 651                 pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
 652         else
 653                 pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));
 654
 655         pci_update_config32(dev, 0x314, 0, 0x743a361b);
 656
 657         /* Set Common Clock Exit Latency in MPC register. */
 658         pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
 659
 660         pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74);
 661
 662         /* Set Invalid Receive Range Check Enable in MPC register. */
 663         pci_or_config32(dev, 0xd8, 1 << 25);
 664
 665         pci_and_config8(dev, 0xf5, 0x0f);
 666
 667         if (rp == 1 || rp == 5 || (is_lp && rp == 6))
 668                 pci_and_config8(dev, 0xf7, ~0x0c);
 669
 670         /* Set EOI forwarding disable. */
 671         pci_or_config32(dev, 0xd4, 1 << 1);
 672
 673         /* Set AER Extended Cap ID to 01h */
 674         u32 aech = CONFIG(PCIEXP_AER) ? 0x10001 : 0;
 675
 676         /* For PCH-LP, set Next Cap Pointer to 200h. */
 677         if (is_lp)
 678                 aech |= 1 << 29;
 679
 680         pci_update_config32(dev, 0x100, ~0xfffff, aech);
 681
 682         if (is_lp) {
 683                 /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
 684                 if (CONFIG(PCIEXP_L1_SUB_STATE))
 685                         pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
 686                 else
 687                         pci_update_config32(dev, 0x200, ~0xfffff, 0);
 688         }
 689
 690         /* Read and write back write-once capability registers. */
 691         pci_update_config32(dev, 0x34, ~0, 0);
 692         pci_update_config32(dev, 0x40, ~0, 0);
 693         pci_update_config32(dev, 0x80, ~0, 0);
 694         pci_update_config32(dev, 0x90, ~0, 0);
 695 }
 696
 697 static void pch_pcie_init(struct device *dev)
 698 {
 699         printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
 700
 701         /* Enable SERR */
 702         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 703
 704         /* Enable Bus Master */
 705         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 706
 707         /* Set Cache Line Size to 0x10 */
 708         // This has no effect but the OS might expect it
 709         pci_write_config8(dev, 0x0c, 0x10);
 710
 711         pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
 712
 713         /* Clear errors in status registers */
 714         pci_update_config16(dev, 0x06, ~0, 0);
 715         pci_update_config16(dev, 0x1e, ~0, 0);
 716 }
 717
 718 static void pch_pcie_enable(struct device *dev)
 719 {
 720         /* Add this device to the root port config structure. */
 721         root_port_init_config(dev);
 722
 723         /* Check to see if this Root Port should be disabled. */
 724         root_port_check_disable(dev);
 725
 726         /* Power Management init before enumeration */
 727         if (dev->enabled)
 728                 pch_pcie_early(dev);
 729
 730         /*
 731          * When processing the last PCIe root port we can now
 732          * update the Root Port Function Number and Hide register.
 733          */
 734         if (root_port_is_last(dev))
 735                 root_port_commit_config();
 736 }
 737
 738 static struct device_operations device_ops = {
 739         .read_resources         = pci_bus_read_resources,
 740         .set_resources          = pci_dev_set_resources,
 741         .enable_resources       = pci_bus_enable_resources,
 742         .init                   = pch_pcie_init,
 743         .enable                 = pch_pcie_enable,
 744         .scan_bus               = pciexp_scan_bridge,
 745         .ops_pci                = &pci_dev_ops_pci,
 746 };
 747
 748 static const unsigned short pci_device_ids[] = {
 749         PCI_DID_INTEL_LPT_H_PCIE_RP1,
 750         PCI_DID_INTEL_LPT_H_PCIE_RP2,
 751         PCI_DID_INTEL_LPT_H_PCIE_RP3,
 752         PCI_DID_INTEL_LPT_H_PCIE_RP4,
 753         PCI_DID_INTEL_LPT_H_PCIE_RP5,
 754         PCI_DID_INTEL_LPT_H_PCIE_RP6,
 755         PCI_DID_INTEL_LPT_H_PCIE_RP7,
 756         PCI_DID_INTEL_LPT_H_PCIE_RP8,
 757         PCI_DID_INTEL_LPT_H_PCIE_RP1_9,
 758         PCI_DID_INTEL_LPT_H_PCIE_RP2_9,
 759         PCI_DID_INTEL_LPT_H_PCIE_RP3_9,
 760         PCI_DID_INTEL_LPT_H_PCIE_RP4_9,
 761         PCI_DID_INTEL_LPT_H_PCIE_RP5_9,
 762         PCI_DID_INTEL_LPT_H_PCIE_RP6_9,
 763         PCI_DID_INTEL_LPT_H_PCIE_RP7_9,
 764         PCI_DID_INTEL_LPT_H_PCIE_RP8_9,
 765         PCI_DID_INTEL_LPT_LP_PCIE_RP1,
 766         PCI_DID_INTEL_LPT_LP_PCIE_RP2,
 767         PCI_DID_INTEL_LPT_LP_PCIE_RP3,
 768         PCI_DID_INTEL_LPT_LP_PCIE_RP4,
 769         PCI_DID_INTEL_LPT_LP_PCIE_RP5,
 770         PCI_DID_INTEL_LPT_LP_PCIE_RP6,
 771         0
 772 };
 773
 774 static const struct pci_driver pch_pcie __pci_driver = {
 775         .ops     = &device_ops,
 776         .vendor  = PCI_VID_INTEL,
 777         .devices = pci_device_ids,
 778 };