mb/google/brox/var/jubilant: Disable Tccold Handshake
[coreboot.git] / src / southbridge / intel / lynxpoint / smbus.c
blob036380248db155f38bbfbb9fcb31bcee0b29041e
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/device.h>
4 #include <device/smbus.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/pci_ops.h>
8 #include <device/smbus_host.h>
9 #include <southbridge/intel/common/smbus_ops.h>
10 #include "pch.h"
12 static void pch_smbus_init(struct device *dev)
14 struct resource *res;
16 /* Enable clock gating */
17 pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
19 /* Set Receive Slave Address */
20 res = probe_resource(dev, PCI_BASE_ADDRESS_4);
21 if (res)
22 smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
25 static struct device_operations smbus_ops = {
26 .read_resources = smbus_read_resources,
27 .set_resources = pci_dev_set_resources,
28 .enable_resources = pci_dev_enable_resources,
29 .scan_bus = scan_smbus,
30 .init = pch_smbus_init,
31 .ops_smbus_bus = &lops_smbus_bus,
32 .ops_pci = &pci_dev_ops_pci,
35 static const unsigned short pci_device_ids[] = {
36 PCI_DID_INTEL_LPT_H_SMBUS,
37 PCI_DID_INTEL_LPT_H_SMBUS_9,
38 PCI_DID_INTEL_LPT_LP_SMBUS,
39 PCI_DID_INTEL_WPT_LP_SMBUS,
43 static const struct pci_driver pch_smbus __pci_driver = {
44 .ops = &smbus_ops,
45 .vendor = PCI_VID_INTEL,
46 .devices = pci_device_ids,