src/southbridge/intel/lynxpoint/smi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <console/console.h>
   6 #include <arch/io.h>
   7 #include <cpu/intel/smm_reloc.h>
   8 #include <cpu/x86/smm.h>
   9
  10 #include "pch.h"
  11
  12 void smm_southbridge_clear_state(void)
  13 {
  14         u32 smi_en;
  15
  16         /* Log events from chipset before clearing */
  17         if (CONFIG(ELOG))
  18                 pch_log_state();
  19
  20         smi_en = inl(get_pmbase() + SMI_EN);
  21         if (smi_en & APMC_EN) {
  22                 printk(BIOS_INFO, "SMI# handler already enabled?\n");
  23                 return;
  24         }
  25
  26         /* Dump and clear status registers */
  27         clear_smi_status();
  28         clear_pm1_status();
  29         clear_tco_status();
  30         clear_gpe_status();
  31 }
  32
  33 static void smm_southbridge_enable(uint16_t pm1_events)
  34 {
  35         printk(BIOS_DEBUG, "Enabling SMIs.\n");
  36         /* Configure events */
  37         enable_pm1(pm1_events);
  38         disable_gpe(PME_B0_EN);
  39
  40         /* Enable SMI generation:
  41          *  - on APMC writes (io 0xb2)
  42          *  - on writes to SLP_EN (sleep states)
  43          *  - on writes to GBL_RLS (bios commands)
  44          * No SMIs:
  45          *  - on microcontroller writes (io 0x62/0x66)
  46          *  - on TCO events
  47          */
  48         enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
  49 }
  50
  51 void global_smi_enable(void)
  52 {
  53         smm_southbridge_enable(PWRBTN_EN | GBL_EN);
  54 }