src/vendorcode/amd/opensil/genoa_poc/Makefile.mk

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 subdirs-y += mpio
   4
   5 CPPFLAGS_common += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF
   6
   7 romstage-y += opensil_console.c
   8 romstage-y += romstage.c
   9
  10 ramstage-y += acpi.c
  11 ramstage-y += memmap.c
  12 ramstage-y += opensil_console.c
  13 ramstage-y += ramstage.c
  14
  15 $(obj)/romstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
  16 $(obj)/romstage/vendorcode/amd/opensil/genoa_poc/romstage.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
  17
  18 $(obj)/ramstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas