2 Many Intel southbridges provide a mechanism called Back Up Control Top Swap (`BUC.TS`).
3 This functionality allows to have the southbridge fetch the reset vector or
4 the beginning of the bootblock at a 64K/128/256K offset from the usual top of flash.
6 This can be useful in different ways:
7 - Have a backup bootblock in case of bootblock hacking;
8 - Some vendor BIOS only write protect their bootblock so this tool makes it
9 possible to circumvent this protection to allow flashing and booting coreboot.
11 The BUC.TS status is stored in a nvram bit. To clear it one has to remove the RTC battery.
13 # Operation Description
14 First compile bucts by running make:
18 Then you can view the current system settings:
22 To flip the decode address of the bootblock, by setting `BUC.TS` to 1:
26 To set the behavior the regular mapping, by setting `BUC.TS` to 0
32 Example Bootblock size of 64KB (this is only configurable to be something else
33 like 128 or 256K on PCH Intel targets).
36 +-------------+ -> 0x200000 +-------------+ -> 0xFFFFFFFF +-------------+ -> 0xFFFFFFFF
38 | bootblock_0 | | bootblock_0 | | bootblock_1 |
40 +-------------+ -> 0x1F0000 +-------------+ -> 0xFFFF0000 +-------------+ -> 0xFFFF0000
42 | bootblock_1 | | bootblock_1 | | bootblock_0 |
44 +-------------+ -> 0x1E0000 +-------------+ -> 0xFFFE0000 +-------------+ -> 0xFFFE0000
51 FLASH (2M) Memory Map BUC.TS=0 Memory Map BUC.TS=1