util/inteltool/ahci.c

   1 /* ahci.c: dump AHCI registers */
   2 /* SPDX-License-Identifier: GPL-2.0-only */
   3
   4 #include <stdio.h>
   5 #include <stdlib.h>
   6 #include <inttypes.h>
   7 #include "inteltool.h"
   8
   9 static const char *ghc_regs[] = {
  10         "CAP", "GHC", "IS", "PI",
  11         "VS", "CCC_CTL", "CCC_PORTS", "EM_LOC",
  12         "EM_CTL", "CAP2", "BOHC"
  13 };
  14
  15 static const char *port_ctl_regs[] = {
  16         "PxCLB", "PxCLBU", "PxFB", "PxFBU",
  17         "PxIS", "PxIE", "PxCMD", "Reserved",
  18         "PxTFD", "PxSIG", "PxSSTS", "PxSCTL",
  19         "PxSERR", "PxSACT", "PxCI", "PxSNTF",
  20         "PxFBS", "PxDEVSLP", "Reserved"
  21 };
  22
  23 static const io_register_t sunrise_ahci_cfg_registers[] = {
  24         {0x0, 4, "ID"},
  25         {0x4, 2, "CMD"},
  26         {0x6, 2, "STS"},
  27         {0x8, 1, "RID"},
  28         {0x9, 1, "PI"},
  29         {0xa, 2, "CC"},
  30         {0xc, 1, "CLS"},
  31         {0xd, 1, "MLT"},
  32         {0xe, 1, "HTYPE"},
  33         {0x10, 4, "MXTBA"},
  34         {0x14, 4, "MXPBA"},
  35         {0x20, 4, "AIDPBA"},
  36         {0x24, 4, "ABAR"},
  37         {0x2c, 4, "SS"},
  38         {0x34, 1, "CAP"},
  39         {0x3c, 2, "INTR"},
  40         {0x70, 2, "PID"},
  41         {0x72, 2, "PC"},
  42         {0x74, 2, "PMCS"},
  43         {0x80, 2, "MID"},
  44         {0x82, 2, "MC"},
  45         {0x84, 4, "MA"},
  46         {0x88, 2, "MD"},
  47         {0x90, 4, "MAP"},
  48         {0x94, 4, "PCS"},
  49         {0x9c, 4, "SATAGC"},
  50         {0xa0, 1, "SIRI"},
  51         {0xa4, 4, "SIRD"},
  52         {0xa8, 4, "SATACR0"},
  53         {0xac, 4, "SATACR1"},
  54         {0xc0, 4, "SP"},
  55         {0xd0, 2, "MXID"},
  56         {0xd2, 2, "MXC"},
  57         {0xd4, 4, "MXT"},
  58         {0xd8, 4, "MXP"},
  59         {0xe0, 4, "BFCS"},
  60         {0xe4, 4, "BFTD1"},
  61         {0xe8, 4, "BFTD2"},
  62 };
  63
  64 static const io_register_t sunrise_ahci_sir_registers[] = {
  65         {0x80, 4, "SQUELCH"},
  66         {0x90, 4, "SATA_MPHY_PG"},
  67         {0xa4, 4, "OOBRETR"},
  68 };
  69
  70 #define NUM_GHC (sizeof(ghc_regs)/sizeof(ghc_regs[0]))
  71 #define NUM_PORTCTL (sizeof(port_ctl_regs)/sizeof(port_ctl_regs[0]))
  72
  73 static void print_port(const uint8_t *const mmio, size_t port)
  74 {
  75         size_t i;
  76         printf("\nPort %zu Control Registers:\n", port);
  77         const uint8_t *const mmio_port = mmio + 0x100 + port * 0x80;
  78         for (i = 0; i < 0x80; i += 4) {
  79                 if (i / 4 < NUM_PORTCTL) {
  80                         printf("0x%03zx: 0x%08x (%s)\n",
  81                                (size_t)(mmio_port - mmio) + i,
  82                                read32(mmio_port + i), port_ctl_regs[i / 4]);
  83                 } else if (read32(mmio_port + i)) {
  84                         printf("0x%03zx: 0x%08x (Reserved)\n",
  85                                (size_t)(mmio_port - mmio) + i,
  86                                read32(mmio_port + i));
  87                 }
  88         }
  89 }
  90
  91 int print_ahci(struct pci_dev *ahci)
  92 {
  93         size_t ahci_registers_size = 0, i;
  94         size_t ahci_cfg_registers_size = 0;
  95         const io_register_t *ahci_cfg_registers;
  96         size_t ahci_sir_index_offset = 0, ahci_sir_data_offset;
  97         size_t ahci_sir_registers_size = 0;
  98         const io_register_t *ahci_sir_registers;
  99
 100         if (!ahci) {
 101                 puts("No SATA device found");
 102                 return 0;
 103         }
 104         printf("\n============= AHCI Registers ==============\n\n");
 105
 106         switch (ahci->device_id) {
 107         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA:
 108         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA:
 109                 ahci_registers_size = 0x800;
 110                 ahci_sir_index_offset = 0xa0;
 111                 ahci_cfg_registers = sunrise_ahci_cfg_registers;
 112                 ahci_cfg_registers_size = ARRAY_SIZE(sunrise_ahci_cfg_registers);
 113                 ahci_sir_registers = sunrise_ahci_sir_registers;
 114                 ahci_sir_registers_size = ARRAY_SIZE(sunrise_ahci_sir_registers);
 115                 break;
 116         default:
 117                 ahci_registers_size = 0x400;
 118         }
 119
 120         ahci_sir_data_offset = ahci_sir_index_offset + 4;
 121
 122         printf("\n============= AHCI Configuration Registers ==============\n\n");
 123         for (i = 0; i < ahci_cfg_registers_size; i++) {
 124                 switch (ahci_cfg_registers[i].size) {
 125                 case 4:
 126                         printf("0x%04x: 0x%08x (%s)\n",
 127                                 ahci_cfg_registers[i].addr,
 128                                 pci_read_long(ahci, ahci_cfg_registers[i].addr),
 129                                 ahci_cfg_registers[i].name);
 130                         break;
 131                 case 2:
 132                         printf("0x%04x: 0x%04x     (%s)\n",
 133                                 ahci_cfg_registers[i].addr,
 134                                 pci_read_word(ahci, ahci_cfg_registers[i].addr),
 135                                 ahci_cfg_registers[i].name);
 136                         break;
 137                 case 1:
 138                         printf("0x%04x: 0x%02x       (%s)\n",
 139                                 ahci_cfg_registers[i].addr,
 140                                 pci_read_byte(ahci, ahci_cfg_registers[i].addr),
 141                                 ahci_cfg_registers[i].name);
 142                         break;
 143                 }
 144         }
 145
 146         printf("\n============= SATA Initialization Registers ==============\n\n");
 147         for (i = 0; i < ahci_sir_registers_size; i++) {
 148                 pci_write_byte(ahci, ahci_sir_index_offset, ahci_sir_registers[i].addr);
 149                 switch (ahci_sir_registers[i].size) {
 150                 case 4:
 151                         printf("0x%02x: 0x%08x (%s)\n",
 152                                 ahci_sir_registers[i].addr,
 153                                 pci_read_long(ahci, ahci_sir_data_offset),
 154                                 ahci_sir_registers[i].name);
 155                         break;
 156                 case 2:
 157                         printf("0x%02x: 0x%04x     (%s)\n",
 158                                 ahci_sir_registers[i].addr,
 159                                 pci_read_word(ahci, ahci_sir_data_offset),
 160                                 ahci_sir_registers[i].name);
 161                         break;
 162                 case 1:
 163                         printf("0x%02x: 0x%02x       (%s)\n",
 164                                 ahci_sir_registers[i].addr,
 165                                 pci_read_byte(ahci, ahci_sir_data_offset),
 166                                 ahci_sir_registers[i].name);
 167                         break;
 168                 }
 169         }
 170
 171         const pciaddr_t ahci_phys = ahci->base_addr[5] & ~0x7ULL;
 172         printf("\n============= ABAR ==============\n\n");
 173         printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)ahci_phys);
 174         const uint8_t *const mmio = map_physical(ahci_phys, ahci_registers_size);
 175         if (mmio == NULL) {
 176                 perror("Error mapping MMIO");
 177                 exit(1);
 178         }
 179
 180         puts("Generic Host Control Registers:");
 181         for (i = 0; i < 0x100; i += 4) {
 182                 if (i / 4 < NUM_GHC) {
 183                         printf("0x%03zx: 0x%08x (%s)\n",
 184                                i, read32(mmio + i), ghc_regs[i / 4]);
 185                 } else if (read32(mmio + i)) {
 186                         printf("0x%03zx: 0x%08x (Reserved)\n", i,
 187                                read32(mmio + i));
 188                 }
 189         }
 190
 191         const size_t max_ports = (ahci_registers_size - 0x100) / 0x80;
 192         for (i = 0; i < max_ports; i++) {
 193                 if (read32(mmio + 0x0c) & 1 << i)
 194                         print_port(mmio, i);
 195         }
 196
 197         puts("\nOther registers:");
 198         for (i = 0x500; i < ahci_registers_size; i += 4) {
 199                 if (read32(mmio + i))
 200                         printf("0x%03zx: 0x%08x\n", i, read32(mmio + i));
 201         }
 202
 203         unmap_physical((void *)mmio, ahci_registers_size);
 204         return 0;
 205 }