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mb/google/fatcat: Move CSE sync at payload
[coreboot.git] / util / msrtool / intel_atom.c
blobe220eb0be02d46f51d53cc353f9e5c2a05932fb3
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include "msrtool.h"
4
5 int intel_atom_probe(const struct targetdef *target, const struct cpuid_t *id) {
6 return ((VENDOR_INTEL == id->vendor) &&
7 (0x6 == id->family) &&
8 (0x1c == id->model));
9 }
10
11 const struct msrdef intel_atom_msrs[] = {
12 {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR",
13 "Pentium Processor Machine-Check Exception Address", {
14 { BITS_EOT }
15 }},
16 {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE",
17 "Pentium Processor Machine-Check Exception Type", {
18 { BITS_EOT }
19 }},
20 {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", {
21 { BITS_EOT }
22 }},
23 {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {
24 { BITS_EOT }
25 }},
26 {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBL_CR_POWERON", "", {
27 { BITS_EOT }
28 }},
29 {0xcd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_FSB_FREQ", "Scalable Bus Speed", {
30 { BITS_EOT }
31 }},
32 {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
33 { BITS_EOT }
34 }},
35 {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BBL_CR_CTL3", "", {
36 { BITS_EOT }
37 }},
38 {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
39 { 63, 19, RESERVED },
40 { 44, 5, "Maximum Bus Ratio", "R/O", PRESENT_DEC, {
41 { BITVAL_EOT }
42 }},
43 { 39, 24, RESERVED },
44 { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX, {
45 { BITVAL_EOT }
46 }},
47 { BITS_EOT }
48 }},
49 {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", {
50 { BITS_EOT }
51 }},
52 {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE0", "", {
53 { BITS_EOT }
54 }},
55 {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK0", "", {
56 { BITS_EOT }
57 }},
58 {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE1", "", {
59 { BITS_EOT }
60 }},
61 {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK1", "", {
62 { BITS_EOT }
63 }},
64 {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE2", "", {
65 { BITS_EOT }
66 }},
67 {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK2", "", {
68 { BITS_EOT }
69 }},
70 {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE3", "", {
71 { BITS_EOT }
72 }},
73 {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK3", "", {
74 { BITS_EOT }
75 }},
76 {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE4", "", {
77 { BITS_EOT }
78 }},
79 {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK4", "", {
80 { BITS_EOT }
81 }},
82 {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE5", "", {
83 { BITS_EOT }
84 }},
85 {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK5", "", {
86 { BITS_EOT }
87 }},
88 {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE6", "", {
89 { BITS_EOT }
90 }},
91 {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK6", "", {
92 { BITS_EOT }
93 }},
94 #if 0
95 {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE7", "", {
96 { BITS_EOT }
97 }},
98 {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK7", "", {
99 { BITS_EOT }
100 }},
101 #endif
102 {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
103 { BITS_EOT }
104 }},
105 {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
106 { BITS_EOT }
107 }},
108 {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
109 { BITS_EOT }
110 }},
111 {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
112 { BITS_EOT }
113 }},
114 {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
115 { BITS_EOT }
116 }},
117 {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
118 { BITS_EOT }
119 }},
120 {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
121 { BITS_EOT }
122 }},
123 {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
124 { BITS_EOT }
125 }},
126 {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
127 { BITS_EOT }
128 }},
129 {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
130 { BITS_EOT }
131 }},
132 {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
133 { BITS_EOT }
134 }},
135 /* if CPUID.01H: ECX[15] = 1 */
136 {0x345, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", {
137 /* Additional info available at Section 17.4.1 of
138 * Intel 64 and IA-32 Architectures Software Developer's
139 * Manual, Volume 3.
140 */
141 { 63, 50, RESERVED },
142 { 13, 1, "Counter width", "R/O", PRESENT_BIN, {
143 { MSR1(0), "Nothing" },
144 { MSR1(1), "Full width of counter writable via IA32_A_PMCx" },
145 { BITVAL_EOT }
146 }},
147 { 12, 1, "SMM_FREEZE", "R/O", PRESENT_BIN, {
148 { MSR1(0), "Nothing" },
149 { MSR1(1), "Freeze while SMM is supported" },
150 { BITVAL_EOT }
151 }},
152 { 11, 4, "PEBS_REC_FORMAT", "R/O", PRESENT_HEX, {
153 { BITVAL_EOT }
154 }},
155 { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, {
156 { BITVAL_EOT }
157 }},
158 { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, {
159 { BITVAL_EOT }
160 }},
161 { 5, 6, "LBR Format", "R/O", PRESENT_HEX, {
162 { BITVAL_EOT }
163 }},
164 { BITS_EOT }
165 }},
166 {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
167 { BITS_EOT }
168 }},
169 {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
170 { BITS_EOT }
171 }},
172 {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
173 { BITS_EOT }
174 }},
175 {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", {
176 { BITS_EOT }
177 }},
178 {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", {
179 { BITS_EOT }
180 }},
181 {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", {
182 { BITS_EOT }
183 }},
184 {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", {
185 { BITS_EOT }
186 }},
187 {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", {
188 { BITS_EOT }
189 }},
190 {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
191 { BITS_EOT }
192 }},
193 {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
194 { BITS_EOT }
195 }},
196 {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
197 { BITS_EOT }
198 }},
199 {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", {
200 { BITS_EOT }
201 }},
202 {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", {
203 { BITS_EOT }
204 }},
205 {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", {
206 { BITS_EOT }
207 }},
208
209 /* ==========================================================================
210 * Per core MSRs
211 * ==========================================================================
212 */
213
214 {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", {
215 { BITS_EOT }
216 }},
217 {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", {
218 { BITS_EOT }
219 }},
220 {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "APIC BASE", {
221 /* In Intel's manual there is MAXPHYWID,
222 * which determine index of highest bit of
223 * APIC Base itself, so marking it as
224 * 'RESERVED'.
225 */
226 { 63, 52, RESERVED },
227 { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN, {
228 { BITVAL_EOT }
229 }},
230 { 10, 1, "x2APIC mode", "R/W", PRESENT_BIN, {
231 { MSR1(0), "x2APIC mode is disabled" },
232 { MSR1(1), "x2APIC mode is enabled" },
233 { BITVAL_EOT }
234 }},
235 { 9, 1, RESERVED },
236 { 8, 1, "BSP Flag", "R/W", PRESENT_BIN, {
237 { BITVAL_EOT }
238 }},
239 { 7, 8, RESERVED },
240 { BITS_EOT }
241 }},
242 /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */
243 {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL",
244 "Control features in Intel 64Processor", {
245 { 63, 48, RESERVED },
246 /* if CPUID.01H: ECX[6] = 1 */
247 { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, {
248 { MSR1(0), "SENTER leaf functions are disabled" },
249 { MSR1(1), "SENTER leaf functions are enabled" },
250 { BITVAL_EOT }
251 }},
252 /* if CPUID.01H: ECX[6] = 1 */
253 { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, {
254 { BITVAL_EOT }
255 }},
256 { 7, 5, RESERVED },
257 /* if CPUID.01H: ECX[5 or 6] = 1 */
258 { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, {
259 /* This bit enables VMX for system executive
260 * that do not require SMX.
261 */
262 { MSR1(0), "VMX outside of SMX operation disabled" },
263 { MSR1(1), "VMX outside of SMX operation enabled" },
264 { BITVAL_EOT }
265 }},
266 { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
267 /* This bit enables a system executive to use
268 * VMX in conjunction with SMX to support Intel
269 * Trusted Execution Technology.
270 */
271 { MSR1(0), "VMX inside of SMX operation disabled" },
272 { MSR1(1), "VMX inside of SMX operation enabled" },
273 { BITVAL_EOT }
274 }},
275 /* if CPUID.01H: ECX[5 or 6] = 1 */
276 { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, {
277 /* Once the Lock bit is set, the contents
278 * of this register cannot be modified.
279 * Therefore the lock bit must be set after
280 * configuring support for Intel Virtualization
281 * Technology and prior transferring control
282 * to an Option ROM or bootloader. Hence, once
283 * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR
284 * contents are preserved across RESET when
285 * PWRGOOD it not deasserted.
286 */
287 { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" },
288 { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" },
289 { BITVAL_EOT }
290 }},
291 { BITS_EOT }
292 }},
293 {0x40, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", {
294 { BITS_EOT }
295 }},
296 {0x41, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "", {
297 { BITS_EOT }
298 }},
299 {0x42, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", {
300 { BITS_EOT }
301 }},
302 {0x43, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "", {
303 { BITS_EOT }
304 }},
305 {0x44, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_FROM_IP", "", {
306 { BITS_EOT }
307 }},
308 {0x45, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_5_FROM_IP", "", {
309 { BITS_EOT }
310 }},
311 {0x46, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_FROM_IP", "", {
312 { BITS_EOT }
313 }},
314 {0x47, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_7_FROM_IP", "", {
315 { BITS_EOT }
316 }},
317 {0x60, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "", {
318 { BITS_EOT }
319 }},
320 {0x61, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "", {
321 { BITS_EOT }
322 }},
323 {0x62, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "", {
324 { BITS_EOT }
325 }},
326 {0x63, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "", {
327 { BITS_EOT }
328 }},
329 {0x64, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_TO_LIP", "", {
330 { BITS_EOT }
331 }},
332 {0x65, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_5_TO_LIP", "", {
333 { BITS_EOT }
334 }},
335 {0x66, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_TO_LIP", "", {
336 { BITS_EOT }
337 }},
338 {0x67, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_7_TO_LIP", "", {
339 { BITS_EOT }
340 }},
341 {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID",
342 "BIOS Update Signature ID (RO)", {
343 { BITS_EOT }
344 }},
345 {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC0",
346 "Performance counter register", {
347 { BITS_EOT }
348 }},
349 {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC1",
350 "Performance counter register", {
351 { BITS_EOT }
352 }},
353 {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", {
354 { BITS_EOT }
355 }},
356 {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", {
357 { BITS_EOT }
358 }},
359 {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", {
360 { BITS_EOT }
361 }},
362 {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", {
363 { BITS_EOT }
364 }},
365 {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", {
366 { BITS_EOT }
367 }},
368 {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
369 { 63, 61, RESERVED },
370 { 2, 1, "MCIP", "R/W", PRESENT_BIN, {
371 /* When set, bit indicates that a machine check has been
372 * generated. If a second machine check is detected while
373 * this bit is still set, the processor enters a shutdown state.
374 * Software should write this bit to 0 after processing
375 * a machine check exception.
376 */
377 { MSR1(0), "Nothing" },
378 { MSR1(1), "Machine check has been generated" },
379 { BITVAL_EOT }
380 }},
381 { 1, 1, "EPIV", "R/W", PRESENT_BIN, {
382 /* When set, bit indicates that the instruction addressed
383 * by the instruction pointer pushed on the stack (when
384 * the machine check was generated) is directly associated
385 * with the error
386 */
387 { MSR1(0), "Nothing" },
388 { MSR1(1), "Instruction addressed directly associated with the error" },
389 { BITVAL_EOT }
390 }},
391 { 0, 1, "RIPV", "R/W", PRESENT_BIN, {
392 /* When set, bit indicates that the instruction addressed
393 * by the instruction pointer pushed on the stack (when
394 * the machine check was generated) can be used to restart
395 * the program. If cleared, the program cannot be reliably restarted
396 */
397 { MSR1(0), "Program cannot be reliably restarted" },
398 { MSR1(1), "Instruction addressed can be used to restart the program" },
399 { BITVAL_EOT }
400 }},
401 { BITS_EOT }
402 }},
403 /* if CPUID.0AH: EAX[15:8] > 0 */
404 {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0",
405 "Performance Event Select Register 0", {
406 { 63, 32, RESERVED },
407 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
408 /* When CMASK is not zero, the corresponding performance
409 * counter 0 increments each cycle if the event count
410 * is greater than or equal to the CMASK.
411 */
412 { BITVAL_EOT }
413 }},
414 { 23, 1, "INV", "R/W", PRESENT_BIN, {
415 { MSR1(0), "CMASK using as is" },
416 { MSR1(1), "CMASK inerting" },
417 { BITVAL_EOT }
418 }},
419 { 22, 1, "EN", "R/W", PRESENT_BIN, {
420 { MSR1(0), "No commence counting" },
421 { MSR1(1), "Commence counting" },
422 { BITVAL_EOT }
423 }},
424 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
425 { BITVAL_EOT }
426 }},
427 { 20, 1, "INT", "R/W", PRESENT_BIN, {
428 { MSR1(0), "Interrupt on counter overflow is disabled" },
429 { MSR1(1), "Interrupt on counter overflow is enabled" },
430 { BITVAL_EOT }
431 }},
432 { 19, 1, "PC", "R/W", PRESENT_BIN, {
433 { MSR1(0), "Disabled pin control" },
434 { MSR1(1), "Enabled pin control" },
435 { BITVAL_EOT }
436 }},
437 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
438 { MSR1(0), "Disabled edge detection" },
439 { MSR1(1), "Enabled edge detection" },
440 { BITVAL_EOT }
441 }},
442 { 17, 1, "OS", "R/W", PRESENT_BIN, {
443 { MSR1(0), "Nothing" },
444 { MSR1(1), "Counts while in privilege level is ring 0" },
445 { BITVAL_EOT }
446 }},
447 { 16, 1, "USR", "R/W", PRESENT_BIN, {
448 { MSR1(0), "Nothing" },
449 { MSR1(1), "Counts while in privilege level is not ring 0" },
450 { BITVAL_EOT }
451 }},
452 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
453 /* Qualifies the microarchitectural condition
454 * to detect on the selected event logic. */
455 { BITVAL_EOT }
456 }},
457 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
458 /* Selects a performance event logic unit. */
459 { BITVAL_EOT }
460 }},
461 { BITS_EOT }
462 }},
463 /* if CPUID.0AH: EAX[15:8] > 0 */
464 {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1",
465 "Performance Event Select Register 1", {
466 { 63, 32, RESERVED },
467 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
468 /* When CMASK is not zero, the corresponding performance
469 * counter 1 increments each cycle if the event count
470 * is greater than or equal to the CMASK.
471 */
472 { BITVAL_EOT }
473 }},
474 { 23, 1, "INV", "R/W", PRESENT_BIN, {
475 { MSR1(0), "CMASK using as is" },
476 { MSR1(1), "CMASK inerting" },
477 { BITVAL_EOT }
478 }},
479 { 22, 1, "EN", "R/W", PRESENT_BIN, {
480 { MSR1(0), "No commence counting" },
481 { MSR1(1), "Commence counting" },
482 { BITVAL_EOT }
483 }},
484 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
485 { BITVAL_EOT }
486 }},
487 { 20, 1, "INT", "R/W", PRESENT_BIN, {
488 { MSR1(0), "Interrupt on counter overflow is disabled" },
489 { MSR1(1), "Interrupt on counter overflow is enabled" },
490 { BITVAL_EOT }
491 }},
492 { 19, 1, "PC", "R/W", PRESENT_BIN, {
493 { MSR1(0), "Disabled pin control" },
494 { MSR1(1), "Enabled pin control" },
495 { BITVAL_EOT }
496 }},
497 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
498 { MSR1(0), "Disabled edge detection" },
499 { MSR1(1), "Enabled edge detection" },
500 { BITVAL_EOT }
501 }},
502 { 17, 1, "OS", "R/W", PRESENT_BIN, {
503 { MSR1(0), "Nothing" },
504 { MSR1(1), "Counts while in privilege level is ring 0" },
505 { BITVAL_EOT }
506 }},
507 { 16, 1, "USR", "R/W", PRESENT_BIN, {
508 { MSR1(0), "Nothing" },
509 { MSR1(1), "Counts while in privilege level is not ring 0" },
510 { BITVAL_EOT }
511 }},
512 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
513 /* Qualifies the microarchitectural condition
514 * to detect on the selected event logic. */
515 { BITVAL_EOT }
516 }},
517 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
518 /* Selects a performance event logic unit. */
519 { BITVAL_EOT }
520 }},
521 { BITS_EOT }
522 }},
523 {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", {
524 { BITS_EOT }
525 }},
526 {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION",
527 "Clock Modulation", {
528 { 63, 59, RESERVED },
529 { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, {
530 { MSR1(0), "On demand Clock Modulation is disabled" },
531 { MSR1(1), "On demand Clock Modulation is enabled" },
532 { BITVAL_EOT }
533 }},
534 { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, {
535 { BITVAL_EOT }
536 }},
537 { 0, 1, RESERVED },
538 { BITS_EOT }
539 }},
540 {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT",
541 "Thermal Interrupt Control", {
542 { BITS_EOT }
543 }},
544 {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS",
545 "Thermal Monitor Status", {
546 { BITS_EOT }
547 }},
548 {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE",
549 "Enable miscellaneous processor features", {
550 { 63, 25, RESERVED },
551 /* Note: [38] bit using for whole package,
552 * while some other bits can be Core or Thread
553 * specific.
554 */
555 { 38, 1, "Turbo Mode", "R/W", PRESENT_BIN, {
556 /* When set to a 0 on processors that support IDA,
557 * CPUID.06H: EAX[1] reports the processor's
558 * support of turbo mode is enabled.
559 */
560 { MSR1(0), "Turbo Mode enabled" },
561 /* When set 1 on processors that support Intel Turbo Boost
562 * technology, the turbo mode feature is disabled and
563 * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
564 */
565 { MSR1(1), "Turbo Mode disabled" },
566 { BITVAL_EOT }
567 /* Note: the power-on default value is used by BIOS to detect
568 * hardware support of turbo mode. If power-on default value is 1,
569 * turbo mode is available in the processor. If power-on default
570 * value is 0, turbo mode not available.
571 */
572 }},
573 { 37, 3, RESERVED },
574 { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, {
575 { BITVAL_EOT }
576 }},
577 { 33, 10, RESERVED },
578 { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, {
579 { BITVAL_EOT }
580 }},
581 { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, {
582 { BITVAL_EOT }
583 }},
584 { 21, 3, RESERVED },
585 { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, {
586 { BITVAL_EOT }
587 }},
588 { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, {
589 { BITVAL_EOT }
590 }},
591 /* Note: [16] bit using for whole package,
592 * while some other bits can be Core or Thread
593 * specific.
594 */
595 { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W",
596 PRESENT_BIN, {
597 { BITVAL_EOT }
598 }},
599 { 15, 3, RESERVED },
600 { 12, 1, "Precise Event Based Sampling Unavailable", "R/O",
601 PRESENT_BIN, {
602 { BITVAL_EOT }
603 }},
604 { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, {
605 { BITVAL_EOT }
606 }},
607 { 10, 3, RESERVED },
608 { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, {
609 { BITVAL_EOT }
610 }},
611 { 6, 3, RESERVED },
612 { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W"
613 , PRESENT_BIN, {
614 { BITVAL_EOT }
615 }},
616 { 2, 2, RESERVED },
617 { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, {
618 { BITVAL_EOT }
619 }},
620 { BITS_EOT }
621 }},
622 {0x1c9, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LASTBRANCH_TOS",
623 "Last Branch Record Stack TOS", {
624 /* Contains an index (bits 0-3) that points to the MSR containing
625 * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680).
626 */
627 { BITS_EOT }
628 }},
629 {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL",
630 "Debug/Trace/Profile Resource Control", {
631 /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */
632 { 63, 49, RESERVED },
633 /* Only if IA32_PERF_CAPABILITIES[12] = 1 */
634 { 14, 1, "FREEZE_WHILE_SMM", "R/O", PRESENT_BIN, {
635 { MSR1(0), "Nothing" },
636 { MSR1(1), "Freeze perfmon and trace messages while in SMM" },
637 { BITVAL_EOT }
638 }},
639 { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, {
640 { MSR1(0), "Nothing" },
641 { MSR1(1), "Logical processor can receive and generate PMI "
642 "on behalf of the uncore" },
643 { BITVAL_EOT }
644 }},
645 /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
646 { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, {
647 { MSR1(0), "Nothing" },
648 { MSR1(1), "Each ENABLE bit of the global counter control MSR "
649 "are frozen (address 0x3bf) on PMI request" },
650 { BITVAL_EOT }
651 }},
652 /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
653 { 11, 1, "FREEZE_LBRS_ON_PMI", "R/O", PRESENT_BIN, {
654 { MSR1(0), "Nothing" },
655 { MSR1(1), "LBR stack is frozen on PMI request" },
656 { BITVAL_EOT }
657 }},
658 { 10, 1, "BTS_OFF_USR", "R/O", PRESENT_BIN, {
659 { MSR1(0), "Nothing" },
660 { MSR1(1), "BTS or BTM is skipped if CPL > 0" },
661 { BITVAL_EOT }
662 }},
663 { 9, 1, "BTS_OFF_OS", "R/O", PRESENT_BIN, {
664 { MSR1(0), "Nothing" },
665 { MSR1(1), "BTS or BTM is skipped if CPL = 0" },
666 { BITVAL_EOT }
667 }},
668 { 8, 1, "BTINT", "R/O", PRESENT_BIN, {
669 { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" },
670 { MSR1(1), "An interrupt is generated by the BTS facility "
671 "when the BTS buffer is full" },
672 { BITVAL_EOT }
673 }},
674 { 7, 1, "BTS", "R/O", PRESENT_BIN, {
675 { MSR1(0), "Logging of BTMs (branch trace messages) "
676 "in BTS buffer is disabled" },
677 { MSR1(1), "Logging of BTMs (branch trace messages) "
678 "in BTS buffer is enabled" },
679 { BITVAL_EOT }
680 }},
681 { 6, 1, "TR", "R/O", PRESENT_BIN, {
682 { MSR1(0), "Branch trace messages are disabled" },
683 { MSR1(1), "Branch trace messages are enabled" },
684 { BITVAL_EOT }
685 }},
686 { 5, 4, RESERVED },
687 { 1, 1, "BTF", "R/O", PRESENT_BIN, {
688 { MSR1(0), "Nothing" },
689 { MSR1(1), "Enabled treating EFLAGS.TF as single-step on "
690 "branches instead of single-step on instructions" },
691 { BITVAL_EOT }
692 }},
693 { 0, 1, "LBR", "R/O", PRESENT_BIN, {
694 { MSR1(0), "Nothing" },
695 { MSR1(1), "Enabled recording a running trace of the most "
696 "recent branches taken by the processor in the LBR stack" },
697 { BITVAL_EOT }
698 }},
699 { BITS_EOT }
700 }},
701 {0x1dd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LER_FROM_LIP",
702 "Last Exception Record From Linear IP", {
703 /* Contains a pointer to the last branch instruction
704 * that the processor executed prior to the last exception
705 * that was generated or the last interrupt that was handled.
706 */
707 { BITS_EOT }
708 }},
709 {0x1de, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LER_TO_LIP",
710 "Last Exception Record To Linear IP", {
711 /* This area contains a pointer to the target of the
712 * last branch instruction that the processor executed
713 * prior to the last exception that was generated or
714 * the last interrupt that was handled
715 */
716 { BITS_EOT }
717 }},
718 {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "IA32_PAT", {
719 { 63, 5, RESERVED },
720 { 58, 3, "PA7", "R/W", PRESENT_BIN, {
721 { BITVAL_EOT }
722 }},
723 { 55, 5, RESERVED },
724 { 40, 3, "PA6", "R/W", PRESENT_BIN, {
725 { BITVAL_EOT }
726 }},
727 { 47, 5, RESERVED },
728 { 42, 3, "PA5", "R/W", PRESENT_BIN, {
729 { BITVAL_EOT }
730 }},
731 { 39, 5, RESERVED },
732 { 34, 3, "PA4", "R/W", PRESENT_BIN, {
733 { BITVAL_EOT }
734 }},
735 { 31, 5, RESERVED },
736 { 26, 3, "PA3", "R/W", PRESENT_BIN, {
737 { BITVAL_EOT }
738 }},
739 { 23, 5, RESERVED },
740 { 18, 3, "PA2", "R/W", PRESENT_BIN, {
741 { BITVAL_EOT }
742 }},
743 { 15, 5, RESERVED },
744 { 10, 3, "PA1", "R/W", PRESENT_BIN, {
745 { BITVAL_EOT }
746 }},
747 { 7, 5, RESERVED },
748 { 2, 3, "PA0", "R/W", PRESENT_BIN, {
749 { BITVAL_EOT }
750 }},
751 { BITS_EOT }
752 }},
753 /* if CPUID.0AH: EDX[4:0] > 0 */
754 {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function "
755 "Performance Counter Register 0: Counts Instr_Retired.Any", {
756 /* Also known as MSR_PERF_FIXED_CTR0 */
757 { BITS_EOT }
758 }},
759 /* if CPUID.0AH: EDX[4:0] > 1 */
760 {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function "
761 "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
762 /* Also known as MSR_PERF_FIXED_CTR1 */
763 { BITS_EOT }
764 }},
765 /* if CPUID.0AH: EDX[4:0] > 2 */
766 {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function "
767 "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
768 /* Also known as MSR_PERF_FIXED_CTR2 */
769 { BITS_EOT }
770 }},
771 /* if CPUID.0AH: EAX[7:0] > 1*/
772 {0x38d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR_CTRL",
773 "Fixed-Function-Counter Control Register", {
774 /* Also known as MSR_PERF_FIXED_CTR_CTRL.
775 * Counter increments while the results of ANDing respective enable bit
776 * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits
777 * in this MSR is true. */
778 { 63, 52, RESERVED },
779 { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, {
780 { MSR1(0), "Nothing" },
781 { MSR1(1), "PMI when fixed counter 2 overflows is enabled" },
782 { BITVAL_EOT }
783 }},
784 /* if CPUID.0AH EAX[7:0] > 2 */
785 { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
786 { MSR1(0), "Counter only increments the associated event "
787 "conditions occurring in the logical processor "
788 "which programmed the MSR" },
789 { MSR1(1), "Counting the associated event conditions "
790 "occurring across all logical processors sharing "
791 "a processor core" },
792 { BITVAL_EOT }
793 }},
794 { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
795 { MSR1(0), "Nothing" },
796 { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" },
797 { BITVAL_EOT }
798 }},
799 { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, {
800 { MSR1(0), "Nothing" },
801 { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" },
802 { BITVAL_EOT }
803 }},
804 { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, {
805 { MSR1(0), "Nothing" },
806 { MSR1(1), "PMI when fixed counter 1 overflows is enabled" },
807 { BITVAL_EOT }
808 }},
809 /* if CPUID.0AH: EAX[7:0] > 2 */
810 { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
811 { MSR1(0), "Counter only increments the associated event "
812 "conditions occurring in the logical processor "
813 "which programmed the MSR" },
814 { MSR1(1), "Counting the associated event conditions "
815 "occurring across all logical processors sharing "
816 "a processor core" },
817 { BITVAL_EOT }
818 }},
819 { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
820 { MSR1(0), "Nothing" },
821 { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" },
822 { BITVAL_EOT }
823 }},
824 { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, {
825 { MSR1(0), "Nothing" },
826 { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" },
827 { BITVAL_EOT }
828 }},
829 { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, {
830 { MSR1(0), "Nothing" },
831 { MSR1(1), "PMI when fixed counter 0 overflows is enabled" },
832 { BITVAL_EOT }
833 }},
834 /* if CPUID.0AH: EAX[7:0] > 2 */
835 { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
836 { MSR1(0), "Counter only increments the associated event "
837 "conditions occurring in the logical processor "
838 "which programmed the MSR" },
839 { MSR1(1), "Counting the associated event conditions "
840 "occurring across all logical processors sharing "
841 "a processor core" },
842 { BITVAL_EOT }
843 }},
844 { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
845 { MSR1(0), "Nothing" },
846 { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" },
847 { BITVAL_EOT }
848 }},
849 { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, {
850 { MSR1(0), "Nothing" },
851 { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" },
852 { BITVAL_EOT }
853 }},
854 { BITS_EOT }
855 }},
856 /* if CPUID.0AH: EAX[7:0] > 0 */
857 {0x38e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_GLOBAL_STATUS",
858 "Global Performance Counter Status", {
859 /* Also known as MSR_PERF_GLOBAL_STATUS */
860 /* if CPUID.0AH: EAX[7:0] > 0 */
861 { 63, 1, "CondChg: Status bits of this register has changed",
862 "R/O", PRESENT_BIN, {
863 { BITVAL_EOT }
864 }},
865 /* if CPUID.0AH: EAX[7:0] > 0 */
866 { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status",
867 "R/O", PRESENT_BIN, {
868 { BITVAL_EOT }
869 }},
870 /* if CPUID.0AH: EAX[7:0] > 2 */
871 { 61, 1, "Ovf_Uncore: Uncore counter overflow status",
872 "R/O", PRESENT_BIN, {
873 { BITVAL_EOT }
874 }},
875 { 60, 26, RESERVED },
876 /* if CPUID.0AH: EAX[7:0] > 1 */
877 { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2",
878 "R/O", PRESENT_BIN, {
879 { BITVAL_EOT }
880 }},
881 /* if CPUID.0AH: EAX[7:0] > 1 */
882 { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1",
883 "R/O", PRESENT_BIN, {
884 { BITVAL_EOT }
885 }},
886 /* if CPUID.0AH: EAX[7:0] > 1 */
887 { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0",
888 "R/O", PRESENT_BIN, {
889 { BITVAL_EOT }
890 }},
891 { 31, 28, RESERVED },
892 /* presented only in 06_2EH Nehalem model */
893 { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, {
894 { BITVAL_EOT }
895 }},
896 /* presented only in 06_2EH Nehalem model */
897 { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, {
898 { BITVAL_EOT }
899 }},
900 /* if CPUID.0AH: EAX[7:0] > 0 */
901 { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, {
902 { BITVAL_EOT }
903 }},
904 /* if CPUID.0AH: EAX[7:0] > 0 */
905 { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, {
906 { BITVAL_EOT }
907 }},
908 { BITS_EOT }
909 }},
910 /* if CPUID.0AH: EAX[7:0] > 0 */
911 {0x38f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_CTL",
912 "Global Performance Counter Control", {
913 /* Counter increments while the result of ANDing respective
914 * enable bit in this MSR with corresponding OS or USR bits
915 * in general-purpose or fixed counter control MSR is true.
916 */
917 { 63, 29, RESERVED },
918 /* if CPUID.0AH: EAX[7:0] > 1 */
919 { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, {
920 { BITVAL_EOT }
921 }},
922 /* if CPUID.0AH: EAX[7:0] > 1 */
923 { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, {
924 { BITVAL_EOT }
925 }},
926 /* if CPUID.0AH: EAX[7:0] > 1 */
927 { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, {
928 { BITVAL_EOT }
929 }},
930 { 31, 30, RESERVED },
931 /* if CPUID.0AH: EAX[7:0] > 0 */
932 { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, {
933 { BITVAL_EOT }
934 }},
935 /* if CPUID.0AH: EAX[7:0] > 0 */
936 { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, {
937 { BITVAL_EOT }
938 }},
939 { BITS_EOT }
940 }},
941 /* if CPUID.0AH: EAX[7:0] > 0 */
942 {0x390, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_OVF_CTL",
943 "Global Performance Counter Overflow Control", {
944 /* if CPUID.0AH: EAX[7:0] > 0 */
945 { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, {
946 { BITVAL_EOT }
947 }},
948 /* if CPUID.0AH: EAX[7:0] > 0 */
949 { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, {
950 { BITVAL_EOT }
951 }},
952 /* Presented only in 06_2EH Nehalem model */
953 { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, {
954 { BITVAL_EOT }
955 }},
956 { 60, 26, RESERVED },
957 /* if CPUID.0AH: EAX[7:0] > 1 */
958 { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, {
959 { BITVAL_EOT }
960 }},
961 /* if CPUID.0AH: EAX[7:0] > 1 */
962 { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, {
963 { BITVAL_EOT }
964 }},
965 /* if CPUID.0AH: EAX[7:0] > 1 */
966 { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, {
967 { BITVAL_EOT }
968 }},
969 { 31, 30, RESERVED },
970 /* if CPUID.0AH: EAX[7:0] > 0 */
971 { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, {
972 { BITVAL_EOT }
973 }},
974 /* if CPUID.0AH: EAX[7:0] > 0 */
975 { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, {
976 { BITVAL_EOT }
977 }},
978 { BITS_EOT }
979 }},
980 /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures
981 * Software Developer's Manual, Volume 3,
982 * "Precise Event Based Sampling (PEBS)".
983 */
984 {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PEBS_ENABLE", "PEBS Control", {
985 { 63, 28, RESERVED },
986 { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, {
987 { MSR1(0), "Disabled" },
988 { MSR1(1), "Enabled" },
989 { BITVAL_EOT }
990 }},
991 { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, {
992 { MSR1(0), "Disabled" },
993 { MSR1(1), "Enabled" },
994 { BITVAL_EOT }
995 }},
996 { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, {
997 { MSR1(0), "Disabled" },
998 { MSR1(1), "Enabled" },
999 { BITVAL_EOT }
1000 }},
1001 { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, {
1002 { MSR1(0), "Disabled" },
1003 { MSR1(1), "Enabled" },
1004 { BITVAL_EOT }
1005 }},
1006 { 31, 28, RESERVED },
1007 { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, {
1008 { MSR1(0), "Disabled" },
1009 { MSR1(1), "Enabled" },
1010 { BITVAL_EOT }
1011 }},
1012 { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, {
1013 { MSR1(0), "Disabled" },
1014 { MSR1(1), "Enabled" },
1015 { BITVAL_EOT }
1016 }},
1017 { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, {
1018 { MSR1(0), "Disabled" },
1019 { MSR1(1), "Enabled" },
1020 { BITVAL_EOT }
1021 }},
1022 { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, {
1023 { MSR1(0), "Disabled" },
1024 { MSR1(1), "Enabled" },
1025 { BITVAL_EOT }
1026 }},
1027 { BITS_EOT }
1028 }},
1029 #if 0
1030 {0x480, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_BASIC",
1031 "Reporting Register of Basic VMX Capabilities", {
1032 /* Additional info available at
1033 * Appendix A.1, "Basic VMX Information" */
1034 { 63, 10, RESERVED },
1035 { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, {
1036 { BITVAL_EOT }
1037 }},
1038 { 49, 1, "Support of dual-treatment of system-management functions",
1039 "R/O", PRESENT_BIN, {
1040 { BITVAL_EOT }
1041 }},
1042 { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, {
1043 { BITVAL_EOT }
1044 }},
1045 { 47, 3, RESERVED },
1046 { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, {
1047 { BITVAL_EOT }
1048 }},
1049 { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, {
1050 { BITVAL_EOT }
1051 }},
1052 { BITS_EOT }
1053 }},
1054 {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS",
1055 "Capability Reporting Register of "
1056 "Pin-based VM-execution Controls", {
1057 /* Additional info available at Appendix A.3,
1058 * "VM-Execution Controls" */
1059 { BITS_EOT }
1060 }},
1061 {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS",
1062 "Capability Reporting Register of "
1063 "Primary Processor-based VM-execution Controls", {
1064 /* Additional info available at Appendix A.3,
1065 * "VM-Execution Controls" */
1066 { BITS_EOT }
1067 }},
1068 {0x483, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_EXIT_CTLS",
1069 "Capability Reporting Register of VM-exit Controls", {
1070 /* Additional info available at Appendix A.4,
1071 * "VM-Exit Controls" */
1072 { BITS_EOT }
1073 }},
1074 {0x484, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS",
1075 "Capability Reporting Register of VM-entry Controls", {
1076 /* Additional info available at Appendix A.5,
1077 * "VM-Entry Controls" */
1078 { BITS_EOT }
1079 }},
1080 {0x485, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_MISC",
1081 "Reporting Register of Miscellaneous VMX Capabilities", {
1082 /* Additional info available at Appendix A.6,
1083 * "Miscellaneous Data" */
1084 { BITS_EOT }
1085 }},
1086 {0x486, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED0",
1087 "Capability Reporting Register of CR0 Bits Fixed to 0", {
1088 /* Additional info available at Appendix A.7,
1089 * "VMX-Fixed Bits in CR0" */
1090 { BITS_EOT }
1091 }},
1092 {0x487, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED1",
1093 "Capability Reporting Register of CR0 Bits Fixed to 1", {
1094 /* Additional info available at Appendix A.7,
1095 * "VMX-Fixed Bits in CR0" */
1096 { BITS_EOT }
1097 }},
1098 {0x488, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED0",
1099 "Capability Reporting Register of CR4 Bits Fixed to 0", {
1100 /* Additional info available at Appendix A.8,
1101 * "VMX-Fixed Bits in CR4" */
1102 { BITS_EOT }
1103 }},
1104 {0x489, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED1",
1105 "Capability Reporting Register of CR4 Bits Fixed to 1", {
1106 /* Additional info available at Appendix A.8,
1107 * "VMX-Fixed Bits in CR4" */
1108 { BITS_EOT }
1109 }},
1110 {0x48a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_VMCS_ENUM",
1111 "Capability Reporting Register of VMCS Field Enumeration", {
1112 /* Additional info available at Appendix A.9,
1113 * "VMCS Enumeration" */
1114 { BITS_EOT }
1115 }},
1116 {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2",
1117 "Capability Reporting Register of Secondary "
1118 "Processor-based VM-execution Controls", {
1119 /* Additional info available at Appendix A.3,
1120 * "VM-Execution Controls" */
1121 { BITS_EOT }
1122 }},
1123 #endif
1124 {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "DS Save Area", {
1125 /* Additional info available at Section 18.10.4 of Intel 64
1126 * and IA-32 Architectures Software Developer's Manual,
1127 * "Debug Store (DS) Mechanism".
1128 */
1129 { 63, 32, RESERVED }, // reserved if not in IA-32e mode
1130 { 31, 32, "Linear address of DS buffer management area",
1131 "R/W", PRESENT_HEX, {
1132 { BITVAL_EOT }
1133 }},
1134 { BITS_EOT }
1135 }},
1136 { MSR_EOT }
1137 };
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