util/msrtool/geodelx.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include "msrtool.h"
   4
   5 int geodelx_probe(const struct targetdef *target, const struct cpuid_t *id) {
   6         return 5 == id->family && 10 == id->model;
   7 }
   8
   9 const struct msrdef geodelx_msrs[] = {
  10         { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", {
  11                 { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, {
  12                         { MSR1(0), "Reserved" },
  13                         { MSR1(1), "8 MB" },
  14                         { MSR1(2), "16 MB" },
  15                         { MSR1(3), "32 MB" },
  16                         { MSR1(4), "64 MB" },
  17                         { MSR1(5), "128 MB" },
  18                         { MSR1(6), "256 MB" },
  19                         { MSR1(7), "512 MB" },
  20                         { MSR1(8), "1 GB" },
  21                         { MSR1(9), "Reserved" },
  22                         { MSR1(10), "Reserved" },
  23                         { MSR1(11), "Reserved" },
  24                         { MSR1(12), "Reserved" },
  25                         { MSR1(13), "Reserved" },
  26                         { MSR1(14), "Reserved" },
  27                         { MSR1(15), "Reserved" },
  28                         { BITVAL_EOT }
  29                 }},
  30                 { 59, 3, RESERVED },
  31                 { 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, {
  32                         { MSR1(0), "1 Module bank" },
  33                         { MSR1(1), "2 Module banks" },
  34                         { BITVAL_EOT }
  35                 }},
  36                 { 55, 3, RESERVED },
  37                 { 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, {
  38                         { MSR1(0), "2 Component banks" },
  39                         { MSR1(1), "4 Component banks" },
  40                         { BITVAL_EOT }
  41                 }},
  42                 { 51, 1, RESERVED },
  43                 { 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, {
  44                         { MSR1(0), "1 KB" },
  45                         { MSR1(1), "2 KB" },
  46                         { MSR1(2), "4 KB" },
  47                         { MSR1(3), "8 KB" },
  48                         { MSR1(4), "16 KB" },
  49                         { MSR1(5), "32 KB" },
  50                         { MSR1(6), "Reserved" },
  51                         { MSR1(7), "DIMM1 Not Installed" },
  52                         { BITVAL_EOT }
  53                 }},
  54                 { 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, {
  55                         { MSR1(0), "Reserved" },
  56                         { MSR1(1), "8 MB" },
  57                         { MSR1(2), "16 MB" },
  58                         { MSR1(3), "32 MB" },
  59                         { MSR1(4), "64 MB" },
  60                         { MSR1(5), "128 MB" },
  61                         { MSR1(6), "256 MB" },
  62                         { MSR1(7), "512 MB" },
  63                         { MSR1(8), "1 GB" },
  64                         { MSR1(9), "Reserved" },
  65                         { MSR1(10), "Reserved" },
  66                         { MSR1(11), "Reserved" },
  67                         { MSR1(12), "Reserved" },
  68                         { MSR1(13), "Reserved" },
  69                         { MSR1(14), "Reserved" },
  70                         { MSR1(15), "Reserved" },
  71                         { BITVAL_EOT }
  72                 }},
  73                 { 43, 3, RESERVED },
  74                 { 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, {
  75                         { MSR1(0), "1 Module bank" },
  76                         { MSR1(1), "2 Module banks" },
  77                         { BITVAL_EOT }
  78                 }},
  79                 { 39, 3, RESERVED },
  80                 { 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, {
  81                         { MSR1(0), "2 Component banks" },
  82                         { MSR1(1), "4 Component banks" },
  83                         { BITVAL_EOT }
  84                 }},
  85                 { 35, 1, RESERVED },
  86                 { 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, {
  87                         { MSR1(0), "1 KB" },
  88                         { MSR1(1), "2 KB" },
  89                         { MSR1(2), "4 KB" },
  90                         { MSR1(3), "8 KB" },
  91                         { MSR1(4), "16 KB" },
  92                         { MSR1(5), "32 KB" },
  93                         { MSR1(6), "Reserved" },
  94                         { MSR1(7), "DIMM0 Not Installed" },
  95                         { BITVAL_EOT }
  96                 }},
  97                 { 31, 2, RESERVED },
  98                 { 29, 2, "MSR_BA", "Mode Register Set Bank Address", PRESENT_BIN, {
  99                         { MSR1(0), "Program the DIMM Mode Register" },
 100                         { MSR1(1), "Program the DIMM Extended Mode Register" },
 101                         { MSR1(2), "Reserved" },
 102                         { MSR1(3), "Reserved" },
 103                         { BITVAL_EOT }
 104                 }},
 105                 { 27, 1, "RST_DLL", "Mode Register Reset DLL", PRESENT_BIN, {
 106                         { MSR1(0), "Do not reset DLL" },
 107                         { MSR1(1), "Reset DLL" },
 108                         { BITVAL_EOT }
 109                 }},
 110                 { 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, {
 111                         { MSR1(0), "Enable" },
 112                         { MSR1(1), "Disable" },
 113                         { BITVAL_EOT }
 114                 }},
 115                 { 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, {
 116                         { MSR1(0), "Normal" },
 117                         { MSR1(1), "Reduced" },
 118                         { BITVAL_EOT }
 119                 }},
 120                 { 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, {
 121                         { MSR1(0), "Enable" },
 122                         { MSR1(1), "Disable" },
 123                         { BITVAL_EOT }
 124                 }},
 125                 { 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS },
 126                 { 7, 4, "REF_STAG", "Refresh Staggering", PRESENT_DEC, NOBITS },
 127                 { 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS },
 128                 { 2, 1, RESERVED },
 129                 { 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS },
 130                 { 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS },
 131                 { BITS_EOT }
 132         }},
 133         { 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", {
 134                 { 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS },
 135                 { 55, 3, RESERVED },
 136                 { 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, {
 137                         { MSR1(0), "ADDR[18]" },
 138                         { MSR1(1), "ADDR[19]" },
 139                         { MSR1(2), "ADDR[20]" },
 140                         { MSR1(3), "ADDR[21]" },
 141                         { BITVAL_EOT }
 142                 }},
 143                 { 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, {
 144                         { MSR1(0), "Disabled" },
 145                         { MSR1(1), "Enabled" },
 146                         { BITVAL_EOT }
 147                 }},
 148                 { 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, {
 149                         { MSR1(0), "Disabled" },
 150                         { MSR1(1), "Enabled" },
 151                         { BITVAL_EOT }
 152                 }},
 153                 { 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, {
 154                         { MSR1(0), "Disabled" },
 155                         { MSR1(1), "Enabled" },
 156                         { BITVAL_EOT }
 157                 }},
 158                 { 47, 6, RESERVED },
 159                 { 41, 1, "TRUNC_DIS", "Burst Truncate Disable", PRESENT_BIN, {
 160                         { MSR1(0), "Bursts Enabled" },
 161                         { MSR1(1), "Bursts Disabled" },
 162                         { BITVAL_EOT }
 163                 }},
 164                 { 40, 1, "REORDER_DIS", "Reorder Disable", PRESENT_BIN, {
 165                         { MSR1(0), "Reordering Enabled" },
 166                         { MSR1(1), "Reordering Disabled" },
 167                         { BITVAL_EOT }
 168                 }},
 169                 { 39, 6, RESERVED },
 170                 { 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, {
 171                         { MSR1(0), "Low Order Interleave" },
 172                         { MSR1(1), "High Order Interleave" },
 173                         { BITVAL_EOT }
 174                 }},
 175                 { 32, 1, RESERVED },
 176                 { 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS },
 177                 { 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, {
 178                         { MSR1(0), "Reserved" },
 179                         { MSR1(1), "Reserved" },
 180                         { MSR1(2), "2" },
 181                         { MSR1(3), "3" },
 182                         { MSR1(4), "4" },
 183                         { MSR1(5), "1.5" },
 184                         { MSR1(6), "2.5" },
 185                         { MSR1(7), "3.5" },
 186                         { BITVAL_EOT }
 187                 }},
 188                 { 27, 4, "ACT2ACTREF", "ACT to ACT/REF Period. tRC", PRESENT_DEC, NOBITS },
 189                 { 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_DEC, NOBITS },
 190                 { 19, 1, RESERVED },
 191                 { 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_DEC, NOBITS },
 192                 { 15, 1, RESERVED },
 193                 { 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_DEC, NOBITS },
 194                 { 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_DEC, NOBITS },
 195                 { 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, {
 196                         { MSR1(0), "Invalid value" },
 197                         { MSR1(1), "1" },
 198                         { MSR1(2), "2" },
 199                         { MSR1(3), "3" },
 200                         { BITVAL_EOT }
 201                 }},
 202                 { 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, {
 203                         { MSR1(0), "Invalid value" },
 204                         { MSR1(1), "1" },
 205                         { MSR1(2), "2" },
 206                         { MSR1(3), "3" },
 207                         { BITVAL_EOT }
 208                 }},
 209                 { 3, 4, RESERVED },
 210                 { BITS_EOT }
 211         }},
 212         { 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0x11080001), "MC_CF1017_DATA", "Feature Enables", {
 213                 { 63, 34, RESERVED },
 214                 { 29, 2, "WR_TO_RD", "Write to Read Delay. tWTR", PRESENT_DEC, NOBITS },
 215                 { 27, 1, RESERVED },
 216                 { 26, 3, "RD_TMG_CTL", "Read Timing Control", PRESENT_DEC, NOBITS },
 217                 { 23, 3, RESERVED },
 218                 { 20, 5, "REF2ACT", "Refresh to Activate Delay. tRFC", PRESENT_DEC, NOBITS },
 219                 { 15, 8, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, NOBITS },
 220                 { 7, 5, RESERVED },
 221                 { 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, {
 222                         { MSR1(0), "No delay" },
 223                         { MSR1(1), "1-clock delay for unbuffered DIMMs" },
 224                         { MSR1(2), "2-clock delay" },
 225                         { MSR1(3), "Invalid value" },
 226                         { BITVAL_EOT }
 227                 }},
 228                 { BITS_EOT }
 229         }},
 230         { 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", {
 231                 { 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS },
 232                 { 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS },
 233                 { BITS_EOT }
 234         }},
 235         { 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", {
 236                 { 63, 28, RESERVED },
 237                 { 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, NOBITS },
 238                 { 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, NOBITS },
 239                 { 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, NOBITS },
 240                 { 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, NOBITS },
 241                 { 31, 32, RESERVED },
 242                 { BITS_EOT }
 243         }},
 244         { 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x1300), "MC_CFCLK_DBUG", "Clocking and Debug", {
 245                 { 63, 29, RESERVED },
 246                 { 34, 1, "B2B_DIS", "Back-to-Back Command Disable", PRESENT_BIN, {
 247                         { MSR1(0), "Allow back-to-back commands" },
 248                         { MSR1(1), "Disable back-to-back commands" },
 249                         { BITVAL_EOT }
 250                 }},
 251                 { 33, 1, "MTEST_RBEX_EN", "MTEST RBEX Enable", PRESENT_BIN, {
 252                         { MSR1(0), "Disable" },
 253                         { MSR1(1), "Enable" },
 254                         { BITVAL_EOT }
 255                 }},
 256                 { 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, {
 257                         { MSR1(0), "Disable" },
 258                         { MSR1(1), "Enable" },
 259                         { BITVAL_EOT }
 260                 }},
 261                 { 31, 15, RESERVED },
 262                 { 16, 1, "FORCE_PRE", "Force Precharge-all", PRESENT_BIN, {
 263                         { MSR1(0), "Disable" },
 264                         { MSR1(1), "Enable" },
 265                         { BITVAL_EOT }
 266                 }},
 267                 { 15, 3, RESERVED },
 268                 { 12, 1, "TRISTATE_DIS", "TRI-STATE Disable", PRESENT_BIN, {
 269                         { MSR1(0), "Tri-stating enabled" },
 270                         { MSR1(1), "Tri-stating disabled" },
 271                         { BITVAL_EOT }
 272                 }},
 273                 { 11, 2, RESERVED },
 274                 { 9, 1, "MASK_CKE1", "CKE1 Mask", PRESENT_BIN, {
 275                         { MSR1(0), "CKE1 output enable unmasked" },
 276                         { MSR1(1), "CKE1 output enable masked" },
 277                         { BITVAL_EOT }
 278                 }},
 279                 { 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, {
 280                         { MSR1(0), "CKE0 output enable unmasked" },
 281                         { MSR1(1), "CKE0 output enable masked" },
 282                         { BITVAL_EOT }
 283                 }},
 284                 { 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, {
 285                         { MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" },
 286                         { MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" },
 287                         { BITVAL_EOT }
 288                 }},
 289                 { 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, {
 290                         { MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" },
 291                         { MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" },
 292                         { BITVAL_EOT }
 293                 }},
 294                 { 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, {
 295                         { MSR1(0), "MA and BA output enable unmasked" },
 296                         { MSR1(1), "MA and BA output enable masked" },
 297                         { BITVAL_EOT }
 298                 }},
 299                 { 4, 5, RESERVED },
 300                 { BITS_EOT }
 301         }},
 302         { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", {
 303                 { 63, 1, "EN", "Enable", PRESENT_DEC, {
 304                         { MSR1(0), "Use default values" },
 305                         { MSR1(1), "Use value in bits [62:0]" },
 306                         { BITVAL_EOT }
 307                 }},
 308                 { 62, 1, "B_DQ", "Buffer Control for DQ DQS DQM TLA drive", PRESENT_DEC, {
 309                         { MSR1(1), "Half power" },
 310                         { MSR1(0), "Quarter power" },
 311                         { BITVAL_EOT }
 312                 }},
 313                 { 61, 1, "B_CMD", "Buffer Control for RAS CAS CKE CS WE drive", PRESENT_DEC, {
 314                         { MSR1(1), "Half power" },
 315                         { MSR1(0), "Quarter power" },
 316                         { BITVAL_EOT }
 317                 }},
 318                 { 60, 1, "B_MA", "Buffer Control for MA BA drive", PRESENT_DEC, {
 319                         { MSR1(0), "Half power" },
 320                         { MSR1(1), "Full power" },
 321                         { BITVAL_EOT }
 322                 }},
 323                 { 59, 1, "SDCLK_SET", "SDCLK Setup", PRESENT_DEC, {
 324                         { MSR1(0), "Full SDCLK setup" },
 325                         { MSR1(1), "Half SDCLK setup for control signals" },
 326                         { BITVAL_EOT }
 327                 }},
 328                 { 58, 3, "DDR_RLE", "DDR read latch enable position", PRESENT_DEC, NOBITS },
 329                 { 55, 1, "SDCLK_DIS", "SDCLK disable [1,3,5]", PRESENT_DEC, {
 330                         { MSR1(0), "All SDCLK output" },
 331                         { MSR1(1), "SDCLK[0,2,4] output only" },
 332                         { BITVAL_EOT }
 333                 }},
 334                 { 54, 3, "TLA1_OA", "TLA hint pin output adjust", PRESENT_DEC, NOBITS },
 335                 { 51, 2, "D_TLA1", "Output delay for TLA1", PRESENT_DEC, NOBITS },
 336                 { 49, 2, "D_TLA0", "Output delay for TLA0", PRESENT_DEC, NOBITS },
 337                 { 47, 2, "D_DQ_E", "Output delay for DQ DQM - even byte lanes", PRESENT_DEC, NOBITS },
 338                 { 45, 2, "D_DQ_O", "Output delay for DQ DQM - odd byte lanes", PRESENT_DEC, NOBITS },
 339                 { 43, 2, RESERVED},
 340                 { 41, 2, "D_SDCLK", "Output delay for SDCLK", PRESENT_DEC, NOBITS },
 341                 { 39, 2, "D_CMD_O", "Output delay for CKE CS RAS CAS WE - odd bits", PRESENT_DEC, NOBITS },
 342                 { 37, 2, "D_CMD_E", "Output delay for CKE CS RAS CAS WE - even bits", PRESENT_DEC, NOBITS },
 343                 { 35, 2, "D_MA_O", "Output delay for BA MA - odd bits", PRESENT_DEC, NOBITS },
 344                 { 33, 2, "D_MA_E", "Output delay for BA MA - even bits", PRESENT_DEC, NOBITS },
 345                 { 31, 2, "D_PCI_O", "Output delay for pci_ad IRQ13 SUSPA# INTA# - odd bits", PRESENT_DEC, NOBITS },
 346                 { 29, 2, "D_PCI_E", "Output delay for pci_ad IRQ13 SUSPA# INTA# - even bits", PRESENT_DEC, NOBITS },
 347                 { 27, 2, "D_DOTCLK", "Output delay for DOTCLK", PRESENT_DEC, NOBITS },
 348                 { 25, 2, "D_DRGB_O", "Output delay for DRGB[31:0] - odd bits", PRESENT_DEC, NOBITS },
 349                 { 23, 2, "D_DRGB_E", "Output delay for DRGB[31:0] HSYNC VSYNC DISPEN VDDEN LDE_MOD - even bits", PRESENT_DEC, NOBITS },
 350                 { 21, 2, "D_PCI_IN", "Input delay for pci_ad CBE# PAR STOP# FRAME# IRDY# TRDY# DEVSEL# REQ# GNT# CIS", PRESENT_DEC, NOBITS },
 351                 { 19, 2, "D_TDBGI", "Input delay for TDBGI", PRESENT_DEC, NOBITS },
 352                 { 17, 2, "D_VIP", "Input delay for VID[15:0] VIP_HSYNC VIP_VSYNC", PRESENT_DEC, NOBITS },
 353                 { 15, 2, "D_VIPCLK", "Input delay for VIPCLK", PRESENT_DEC, NOBITS },
 354                 { 13, 1, "H_SDCLK", "Half SDCLK hold select (for cmd addr)", PRESENT_DEC, {
 355                         { MSR1(1), "Half SDCLK setup for MA and BA" },
 356                         { MSR1(0), "Full SDCLK setup" },
 357                         { BITVAL_EOT }
 358                 }},
 359                 { 12, 2, "PLL_FD_DEL", "PLL Feedback Delay", PRESENT_BIN, {
 360                         { MSR1(0), "No feedback delay" },
 361                         { MSR1(1), "~350 ps" },
 362                         { MSR1(2), "~700 ps" },
 363                         { MSR1(3), "~1100 ps (Max feedback delay)" },
 364                         { BITVAL_EOT }
 365                 }},
 366                 { 10, 5, RESERVED },
 367                 { 5, 1, "DLL_OV", "DLL Override (to DLL)", PRESENT_DEC, NOBITS },
 368                 { 4, 5, "DLL_OVS/RSDA", "DLL Override Setting or Read Strobe Delay Adjust", PRESENT_DEC, NOBITS },
 369                 { BITS_EOT }
 370         }},
 371         { 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", {
 372                 { 63, 20, RESERVED },
 373                 { 43, 5, "GLIUMULT", "GLIU Multiplier", PRESENT_DEC, NOBITS },
 374                 { 38, 1, "GLIUDIV", "GLIU Divide", PRESENT_DEC, {
 375                         { MSR1(0), "Do not predivide input" },
 376                         { MSR1(1), "Divide by 2" },
 377                         { BITVAL_EOT }
 378                 }},
 379                 { 37, 5, "COREMULT", "CPU Core Multiplier", PRESENT_DEC, NOBITS },
 380                 { 32, 1, "COREDIV", "CPU Core Divide", PRESENT_DEC, {
 381                         { MSR1(0), "Do not predivide input" },
 382                         { MSR1(1), "Divide by 2" },
 383                         { BITVAL_EOT }
 384                 }},
 385                 { 31, 6, "SWFLAGS", "Flags", PRESENT_BIN, NOBITS },
 386                 { 25, 1, "GLIULOCK", "GLIU PLL Lock", PRESENT_DEC, {
 387                         { MSR1(1), "PLL locked" },
 388                         { MSR1(0), "PLL is not locked" },
 389                         { BITVAL_EOT }
 390                 }},
 391                 { 24, 1, "CORELOCK", "CPU Core PLL Lock", PRESENT_DEC, {
 392                         { MSR1(1), "PLL locked" },
 393                         { MSR1(0), "PLL is not locked" },
 394                         { BITVAL_EOT }
 395                 }},
 396                 { 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS },
 397                 { 15, 1, RESERVED },
 398                 { 14, 1, "GLIUPD", "GLIU PLL Power Down mode", PRESENT_DEC, NOBITS },
 399                 { 13, 1, "COREPD", "CPU Core PLL Power Down mode", PRESENT_DEC, NOBITS },
 400                 { 12, 1, "GLIUBYPASS", "GLIU PLL Bypass", PRESENT_DEC, {
 401                         { MSR1(1), "DOTREF input directly drives the GLIU clock spines" },
 402                         { MSR1(0), "DOTPLL drives the GLIU clock" },
 403                         { BITVAL_EOT }
 404                 }},
 405                 { 11, 1, "COREBYPASS", "CPU Core PLL Bypass", PRESENT_DEC, {
 406                         { MSR1(1), "DOTREF input directly drives the CPU Core clock" },
 407                         { MSR1(0), "DOTPLL drives the CPU Core clock" },
 408                         { BITVAL_EOT }
 409                 }},
 410                 { 10, 1, "LPFEN", "Loop Filter", PRESENT_DEC, {
 411                         { MSR1(1), "Enabled" },
 412                         { MSR1(0), "Disabled" },
 413                         { BITVAL_EOT }
 414                 }},
 415                 { 9, 1, "VA_SEMI_SYNC_MODE", "CPU-GLIU Sync Mode", PRESENT_DEC, {
 416                         { MSR1(1), "CPU does not use GLIU FIFO" },
 417                         { MSR1(0), "The GLIU FIFO is used by the CPU" },
 418                         { BITVAL_EOT }
 419                 }},
 420                 { 8, 1, "PCI_SEMI_SYNC_MODE", "PCI-GLIU Sync Mode", PRESENT_DEC, {
 421                         { MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" },
 422                         { MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" },
 423                         { BITVAL_EOT }
 424                 }},
 425                 { 7, 1, "BOOTSTRAP_PW1", "PW1 bootstrap", PRESENT_DEC, {
 426                         { MSR1(1), "66MHz PCI clock" },
 427                         { MSR1(0), "33MHz PCI clock" },
 428                         { BITVAL_EOT }
 429                 }},
 430                 { 6, 1, "BOOTSTRAP_IRQ13", "IRQ13 bootstrap", PRESENT_DEC, {
 431                         { MSR1(1), "Stall-on-reset debug feature enabled" },
 432                         { MSR1(0), "No stall" },
 433                         { BITVAL_EOT }
 434                 }},
 435                 { 5, 5, "BOOTSTRAPS", "CPU/GLIU frequency select", PRESENT_BIN, NOBITS },
 436                 { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS },
 437                 { BITS_EOT }
 438         }},
 439         { MSR_EOT }
 440 };