MAINTAINERS: Add Maximilian Brune to RISC-V
[coreboot.git] / util / nvramtool / cmos_lowlevel.h
blob3efdbd07752b0fd609bcef4cac64c92deb498abc
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef NVRAMTOOL_CMOS_LOWLEVEL_H
4 #define NVRAMTOOL_CMOS_LOWLEVEL_H
6 #include "common.h"
7 #include "layout.h"
9 typedef struct {
10 void (*init)(void* data);
11 unsigned char (*read)(unsigned addr);
12 void (*write)(unsigned addr, unsigned char value);
13 void (*set_iopl)(int level);
14 } cmos_access_t;
16 typedef enum { HAL_CMOS, HAL_MEMORY } hal_t;
17 void select_hal(hal_t hal, void *data);
19 #define CMOS_AREA_OUT_OF_RANGE (CMOS_RESULT_START + 0)
20 #define CMOS_AREA_OVERLAPS_RTC (CMOS_RESULT_START + 1)
21 #define CMOS_AREA_TOO_WIDE (CMOS_RESULT_START + 2)
23 unsigned long long cmos_read(const cmos_entry_t * e);
24 void cmos_write(const cmos_entry_t * e, unsigned long long value);
25 unsigned char cmos_read_byte(unsigned index);
26 void cmos_write_byte(unsigned index, unsigned char value);
27 void cmos_read_all(unsigned char data[]);
28 void cmos_write_all(unsigned char data[]);
29 void set_iopl(int level);
30 int verify_cmos_op(unsigned bit, unsigned length, cmos_entry_config_t config);
32 #define CMOS_SIZE 256 /* size of CMOS memory in bytes */
33 #define CMOS_RTC_AREA_SIZE 14 /* first 14 bytes control real time clock */
35 /****************************************************************************
36 * verify_cmos_byte_index
38 * Return 1 if 'index' does NOT specify a valid CMOS memory location. Else
39 * return 0.
40 ****************************************************************************/
41 static inline int verify_cmos_byte_index(unsigned index)
43 return (index < CMOS_RTC_AREA_SIZE) || (index >= CMOS_SIZE);
46 #endif /* NVRAMTOOL_CMOS_LOWLEVEL_H */