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soc/intel/alderlake/acpi.c: Don't look up coreboot CPU index
[coreboot.git] / src / soc / intel / alderlake / fsp_params.c
blob853b2f2c0d150bdac82c429d5bf6bc68625066f9
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <console/console.h>
5 #include <cpu/intel/microcode.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/pci_ids.h>
9 #include <fsp/api.h>
10 #include <fsp/fsp_debug_event.h>
11 #include <fsp/ppi/mp_service_ppi.h>
12 #include <fsp/util.h>
13 #include <option.h>
14 #include <intelblocks/irq.h>
15 #include <intelblocks/lpss.h>
16 #include <intelblocks/mp_init.h>
17 #include <intelblocks/pmclib.h>
18 #include <intelblocks/xdci.h>
19 #include <intelpch/lockdown.h>
20 #include <intelblocks/systemagent.h>
21 #include <intelblocks/tcss.h>
22 #include <soc/cpu.h>
23 #include <soc/gpio.h>
24 #include <soc/intel/common/vbt.h>
25 #include <soc/pci_devs.h>
26 #include <soc/pcie.h>
27 #include <soc/ramstage.h>
28 #include <soc/soc_chip.h>
29 #include <stdlib.h>
30 #include <string.h>
31 #include <types.h>
32
33 /* THC assignment definition */
34 #define THC_NONE 0
35 #define THC_0 1
36 #define THC_1 2
37
38 /* SATA DEVSLP idle timeout default values */
39 #define DEF_DMVAL 15
40 #define DEF_DITOVAL 625
41
42 /* VccIn Aux Imon IccMax values in mA */
43 #define MILLIAMPS_TO_AMPS 1000
44 #define ICC_MAX_TDP_45W 34250
45 #define ICC_MAX_TDP_15W_28W 32000
46 #define ICC_MAX_ID_ADL_M_MA 12000
47 #define ICC_MAX_ID_ADL_N_MA 27000
48 #define ICC_MAX_ADL_S 33000
49
50 /*
51 * ME End of Post configuration
52 * 0 - Disable EOP.
53 * 1 - Send in PEI (Applicable for FSP in API mode)
54 * 2 - Send in DXE (Not applicable for FSP in API mode)
55 */
56 enum fsp_end_of_post {
57 EOP_DISABLE = 0,
58 EOP_PEI = 1,
59 EOP_DXE = 2,
60 };
61
62 static const struct slot_irq_constraints irq_constraints[] = {
63 {
64 .slot = SA_DEV_SLOT_CPU_1,
65 .fns = {
66 FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A),
67 },
68 },
69 {
70 .slot = SA_DEV_SLOT_IGD,
71 .fns = {
72 /* INTERRUPT_PIN is RO/0x01 */
73 FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A),
74 },
75 },
76 {
77 .slot = SA_DEV_SLOT_DPTF,
78 .fns = {
79 ANY_PIRQ(SA_DEVFN_DPTF),
80 },
81 },
82 {
83 .slot = SA_DEV_SLOT_IPU,
84 .fns = {
85 /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW,
86 but S0ix fails when not set to 16 (b/193434192) */
87 FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A),
88 },
89 },
90 {
91 .slot = SA_DEV_SLOT_CPU_6,
92 .fns = {
93 FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A),
94 FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C),
95 },
96 },
97 {
98 .slot = SA_DEV_SLOT_TBT,
99 .fns = {
100 ANY_PIRQ(SA_DEVFN_TBT0),
101 ANY_PIRQ(SA_DEVFN_TBT1),
102 ANY_PIRQ(SA_DEVFN_TBT2),
103 ANY_PIRQ(SA_DEVFN_TBT3),
104 },
105 },
106 {
107 .slot = SA_DEV_SLOT_GNA,
108 .fns = {
109 /* INTERRUPT_PIN is RO/0x01 */
110 FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A),
111 },
112 },
113 {
114 .slot = SA_DEV_SLOT_TCSS,
115 .fns = {
116 ANY_PIRQ(SA_DEVFN_TCSS_XHCI),
117 ANY_PIRQ(SA_DEVFN_TCSS_XDCI),
118 },
119 },
120 {
121 .slot = PCH_DEV_SLOT_SIO0,
122 .fns = {
123 DIRECT_IRQ(PCH_DEVFN_I2C6),
124 DIRECT_IRQ(PCH_DEVFN_I2C7),
125 ANY_PIRQ(PCH_DEVFN_THC0),
126 ANY_PIRQ(PCH_DEVFN_THC1),
127 },
128 },
129 {
130 .slot = PCH_DEV_SLOT_SIO6,
131 .fns = {
132 DIRECT_IRQ(PCH_DEVFN_UART3),
133 DIRECT_IRQ(PCH_DEVFN_UART4),
134 DIRECT_IRQ(PCH_DEVFN_UART5),
135 DIRECT_IRQ(PCH_DEVFN_UART6),
136 },
137 },
138 {
139 .slot = PCH_DEV_SLOT_ISH,
140 .fns = {
141 DIRECT_IRQ(PCH_DEVFN_ISH),
142 DIRECT_IRQ(PCH_DEVFN_GSPI2),
143 ANY_PIRQ(PCH_DEVFN_UFS),
144 },
145 },
146 {
147 .slot = PCH_DEV_SLOT_SIO2,
148 .fns = {
149 DIRECT_IRQ(PCH_DEVFN_GSPI3),
150 DIRECT_IRQ(PCH_DEVFN_GSPI4),
151 DIRECT_IRQ(PCH_DEVFN_GSPI5),
152 DIRECT_IRQ(PCH_DEVFN_GSPI6),
153 },
154 },
155 {
156 .slot = PCH_DEV_SLOT_XHCI,
157 .fns = {
158 ANY_PIRQ(PCH_DEVFN_XHCI),
159 DIRECT_IRQ(PCH_DEVFN_USBOTG),
160 ANY_PIRQ(PCH_DEVFN_CNVI_WIFI),
161 },
162 },
163 {
164 .slot = PCH_DEV_SLOT_SIO3,
165 .fns = {
166 DIRECT_IRQ(PCH_DEVFN_I2C0),
167 DIRECT_IRQ(PCH_DEVFN_I2C1),
168 DIRECT_IRQ(PCH_DEVFN_I2C2),
169 DIRECT_IRQ(PCH_DEVFN_I2C3),
170 },
171 },
172 {
173 .slot = PCH_DEV_SLOT_CSE,
174 .fns = {
175 ANY_PIRQ(PCH_DEVFN_CSE),
176 ANY_PIRQ(PCH_DEVFN_CSE_2),
177 ANY_PIRQ(PCH_DEVFN_CSE_IDER),
178 ANY_PIRQ(PCH_DEVFN_CSE_KT),
179 ANY_PIRQ(PCH_DEVFN_CSE_3),
180 ANY_PIRQ(PCH_DEVFN_CSE_4),
181 },
182 },
183 {
184 .slot = PCH_DEV_SLOT_SATA,
185 .fns = {
186 ANY_PIRQ(PCH_DEVFN_SATA),
187 },
188 },
189 {
190 .slot = PCH_DEV_SLOT_SIO4,
191 .fns = {
192 DIRECT_IRQ(PCH_DEVFN_I2C4),
193 DIRECT_IRQ(PCH_DEVFN_I2C5),
194 DIRECT_IRQ(PCH_DEVFN_UART2),
195 },
196 },
197 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
198 {
199 .slot = PCH_DEV_SLOT_EMMC,
200 .fns = {
201 ANY_PIRQ(PCH_DEVFN_EMMC),
202 },
203 },
204 #endif
205 {
206 .slot = PCH_DEV_SLOT_PCIE,
207 .fns = {
208 FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
209 FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
210 FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
211 FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
212 FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
213 FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
214 FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
215 FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
216 },
217 },
218 {
219 .slot = PCH_DEV_SLOT_PCIE_1,
220 .fns = {
221 FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
222 FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
223 FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
224 FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
225 },
226 },
227 {
228 .slot = PCH_DEV_SLOT_SIO5,
229 .fns = {
230 /* UART0 shares an interrupt line with TSN0, so must use
231 a PIRQ */
232 FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A),
233 /* UART1 shares an interrupt line with TSN1, so must use
234 a PIRQ */
235 FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B),
236 DIRECT_IRQ(PCH_DEVFN_GSPI0),
237 DIRECT_IRQ(PCH_DEVFN_GSPI1),
238 },
239 },
240 {
241 .slot = PCH_DEV_SLOT_ESPI,
242 .fns = {
243 ANY_PIRQ(PCH_DEVFN_HDA),
244 ANY_PIRQ(PCH_DEVFN_SMBUS),
245 ANY_PIRQ(PCH_DEVFN_GBE),
246 /* INTERRUPT_PIN is RO/0x01 */
247 FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A),
248 },
249 },
250 };
251
252 static const struct slot_irq_constraints irq_constraints_pch_s[] = {
253 {
254 .slot = SA_DEV_SLOT_CPU_1,
255 .fns = {
256 FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A),
257 FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_1, PCI_INT_B, PIRQ_B),
258 },
259 },
260 {
261 .slot = SA_DEV_SLOT_IGD,
262 .fns = {
263 /* INTERRUPT_PIN is RO/0x01 */
264 FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A),
265 },
266 },
267 {
268 .slot = SA_DEV_SLOT_DPTF,
269 .fns = {
270 ANY_PIRQ(SA_DEVFN_DPTF),
271 },
272 },
273 {
274 .slot = SA_DEV_SLOT_CPU_6,
275 .fns = {
276 FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_D, PIRQ_A),
277 },
278 },
279 {
280 .slot = SA_DEV_SLOT_GNA,
281 .fns = {
282 /* INTERRUPT_PIN is RO/0x01 */
283 FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A),
284 },
285 },
286 {
287 .slot = PCH_DEV_SLOT_SIO6,
288 .fns = {
289 DIRECT_IRQ(PCH_DEVFN_UART3),
290 },
291 },
292 {
293 .slot = PCH_DEV_SLOT_ISH,
294 .fns = {
295 DIRECT_IRQ(PCH_DEVFN_ISH),
296 DIRECT_IRQ(PCH_DEVFN_GSPI2),
297 },
298 },
299 {
300 .slot = PCH_DEV_SLOT_SIO2,
301 .fns = {
302 DIRECT_IRQ(PCH_DEVFN_GSPI3),
303 },
304 },
305 {
306 .slot = PCH_DEV_SLOT_XHCI,
307 .fns = {
308 ANY_PIRQ(PCH_DEVFN_XHCI),
309 DIRECT_IRQ(PCH_DEVFN_USBOTG),
310 ANY_PIRQ(PCH_DEVFN_CNVI_WIFI),
311 },
312 },
313 {
314 .slot = PCH_DEV_SLOT_SIO3,
315 .fns = {
316 DIRECT_IRQ(PCH_DEVFN_I2C0),
317 DIRECT_IRQ(PCH_DEVFN_I2C1),
318 DIRECT_IRQ(PCH_DEVFN_I2C2),
319 DIRECT_IRQ(PCH_DEVFN_I2C3),
320 },
321 },
322 {
323 .slot = PCH_DEV_SLOT_CSE,
324 .fns = {
325 ANY_PIRQ(PCH_DEVFN_CSE),
326 ANY_PIRQ(PCH_DEVFN_CSE_2),
327 ANY_PIRQ(PCH_DEVFN_CSE_IDER),
328 ANY_PIRQ(PCH_DEVFN_CSE_KT),
329 ANY_PIRQ(PCH_DEVFN_CSE_3),
330 ANY_PIRQ(PCH_DEVFN_CSE_4),
331 },
332 },
333 {
334 .slot = PCH_DEV_SLOT_SATA,
335 .fns = {
336 ANY_PIRQ(PCH_DEVFN_SATA),
337 },
338 },
339 {
340 .slot = PCH_DEV_SLOT_SIO4,
341 .fns = {
342 DIRECT_IRQ(PCH_DEVFN_I2C4),
343 DIRECT_IRQ(PCH_DEVFN_I2C5),
344 DIRECT_IRQ(PCH_DEVFN_UART2),
345 },
346 },
347 {
348 .slot = PCH_DEV_SLOT_PCIE,
349 .fns = {
350 FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
351 FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
352 FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
353 FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
354 FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
355 FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
356 FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
357 FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
358 },
359 },
360 {
361 .slot = PCH_DEV_SLOT_PCIE_1,
362 .fns = {
363 FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
364 FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
365 FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
366 FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
367 FIXED_INT_PIRQ(PCH_DEVFN_PCIE13, PCI_INT_A, PIRQ_A),
368 FIXED_INT_PIRQ(PCH_DEVFN_PCIE14, PCI_INT_B, PIRQ_B),
369 FIXED_INT_PIRQ(PCH_DEVFN_PCIE15, PCI_INT_C, PIRQ_C),
370 FIXED_INT_PIRQ(PCH_DEVFN_PCIE16, PCI_INT_D, PIRQ_D),
371 },
372 },
373 {
374 .slot = PCH_DEV_SLOT_PCIE_2,
375 .fns = {
376 FIXED_INT_PIRQ(PCH_DEVFN_PCIE17, PCI_INT_A, PIRQ_A),
377 FIXED_INT_PIRQ(PCH_DEVFN_PCIE18, PCI_INT_B, PIRQ_B),
378 FIXED_INT_PIRQ(PCH_DEVFN_PCIE19, PCI_INT_C, PIRQ_C),
379 FIXED_INT_PIRQ(PCH_DEVFN_PCIE20, PCI_INT_D, PIRQ_D),
380 FIXED_INT_PIRQ(PCH_DEVFN_PCIE21, PCI_INT_A, PIRQ_A),
381 FIXED_INT_PIRQ(PCH_DEVFN_PCIE22, PCI_INT_B, PIRQ_B),
382 FIXED_INT_PIRQ(PCH_DEVFN_PCIE23, PCI_INT_C, PIRQ_C),
383 FIXED_INT_PIRQ(PCH_DEVFN_PCIE24, PCI_INT_D, PIRQ_D),
384 },
385 },
386 {
387 .slot = PCH_DEV_SLOT_PCIE_3,
388 .fns = {
389 FIXED_INT_PIRQ(PCH_DEVFN_PCIE25, PCI_INT_A, PIRQ_A),
390 FIXED_INT_PIRQ(PCH_DEVFN_PCIE26, PCI_INT_B, PIRQ_B),
391 FIXED_INT_PIRQ(PCH_DEVFN_PCIE27, PCI_INT_C, PIRQ_C),
392 FIXED_INT_PIRQ(PCH_DEVFN_PCIE28, PCI_INT_D, PIRQ_D),
393 },
394 },
395 {
396 .slot = PCH_DEV_SLOT_SIO5,
397 .fns = {
398 /* UART0 shares an interrupt line with TSN0, so must use
399 a PIRQ */
400 FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A),
401 /* UART1 shares an interrupt line with TSN1, so must use
402 a PIRQ */
403 FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B),
404 DIRECT_IRQ(PCH_DEVFN_GSPI0),
405 DIRECT_IRQ(PCH_DEVFN_GSPI1),
406 },
407 },
408 {
409 .slot = PCH_DEV_SLOT_ESPI,
410 .fns = {
411 ANY_PIRQ(PCH_DEVFN_HDA),
412 ANY_PIRQ(PCH_DEVFN_SMBUS),
413 ANY_PIRQ(PCH_DEVFN_GBE),
414 /* INTERRUPT_PIN is RO/0x01 */
415 FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A),
416 },
417 },
418 };
419
420 static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
421 {
422 const struct pci_irq_entry *entry = get_cached_pci_irqs();
423 SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
424 size_t pch_total = 0;
425 size_t cfg_count = 0;
426
427 if (!entry)
428 return NULL;
429
430 /* Count PCH devices */
431 while (entry) {
432 if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT)
433 ++pch_total;
434 entry = entry->next;
435 }
436
437 /* Convert PCH device entries to FSP format */
438 config = calloc(pch_total, sizeof(*config));
439 entry = get_cached_pci_irqs();
440 while (entry) {
441 if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) {
442 entry = entry->next;
443 continue;
444 }
445
446 config[cfg_count].Device = PCI_SLOT(entry->devfn);
447 config[cfg_count].Function = PCI_FUNC(entry->devfn);
448 config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
449 config[cfg_count].Irq = entry->irq;
450 ++cfg_count;
451
452 entry = entry->next;
453 }
454
455 *out_count = cfg_count;
456
457 return config;
458 }
459
460 /*
461 * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
462 * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
463 * In order to ensure that mainboard setting does not disable L1 substates
464 * incorrectly, chip config parameter values are offset by 1 with 0 meaning
465 * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
466 * value is set in fsp_params.
467 * 0: Use FSP UPD default
468 * 1: Disable L1 substates
469 * 2: Use L1.1
470 * 3: Use L1.2 (FSP UPD default)
471 */
472 static int get_l1_substate_control(enum L1_substates_control ctl)
473 {
474 if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
475 ctl = L1_SS_L1_2;
476 return ctl - 1;
477 }
478
479 /*
480 * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
481 * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
482 * that the mainboard setting does not disable ASPM incorrectly, chip
483 * config parameter values are offset by 1 with 0 meaning use FSP UPD default.
484 * get_aspm_control() ensures that the right UPD value is set in fsp_params.
485 * 0: Use FSP UPD default
486 * 1: Disable ASPM
487 * 2: L0s only
488 * 3: L1 only
489 * 4: L0s and L1
490 * 5: Auto configuration
491 */
492 static unsigned int get_aspm_control(enum ASPM_control ctl)
493 {
494 if ((ctl > ASPM_AUTO) || (ctl == ASPM_DEFAULT))
495 ctl = ASPM_AUTO;
496 return ctl - 1;
497 }
498
499 /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL
500 SKU's */
501 static uint16_t get_vccin_aux_imon_iccmax(void)
502 {
503 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
504 uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
505 uint8_t tdp;
506
507 switch (mch_id) {
508 case PCI_DID_INTEL_ADL_P_ID_1:
509 case PCI_DID_INTEL_ADL_P_ID_3:
510 case PCI_DID_INTEL_ADL_P_ID_4:
511 case PCI_DID_INTEL_ADL_P_ID_5:
512 case PCI_DID_INTEL_ADL_P_ID_6:
513 case PCI_DID_INTEL_ADL_P_ID_7:
514 case PCI_DID_INTEL_ADL_P_ID_8:
515 case PCI_DID_INTEL_ADL_P_ID_9:
516 case PCI_DID_INTEL_ADL_P_ID_10:
517 case PCI_DID_INTEL_RPL_P_ID_1:
518 case PCI_DID_INTEL_RPL_P_ID_2:
519 case PCI_DID_INTEL_RPL_P_ID_3:
520 case PCI_DID_INTEL_RPL_P_ID_4:
521 tdp = get_cpu_tdp();
522 if (tdp == TDP_45W)
523 return ICC_MAX_TDP_45W;
524 return ICC_MAX_TDP_15W_28W;
525 case PCI_DID_INTEL_ADL_M_ID_1:
526 case PCI_DID_INTEL_ADL_M_ID_2:
527 return ICC_MAX_ID_ADL_M_MA;
528 case PCI_DID_INTEL_ADL_N_ID_1:
529 case PCI_DID_INTEL_ADL_N_ID_2:
530 case PCI_DID_INTEL_ADL_N_ID_3:
531 case PCI_DID_INTEL_ADL_N_ID_4:
532 return ICC_MAX_ID_ADL_N_MA;
533 case PCI_DID_INTEL_ADL_S_ID_1:
534 case PCI_DID_INTEL_ADL_S_ID_3:
535 case PCI_DID_INTEL_ADL_S_ID_8:
536 case PCI_DID_INTEL_ADL_S_ID_10:
537 case PCI_DID_INTEL_ADL_S_ID_11:
538 case PCI_DID_INTEL_ADL_S_ID_12:
539 return ICC_MAX_ADL_S;
540 default:
541 printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n",
542 mch_id);
543 return 0;
544 }
545 }
546
547 __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
548 {
549 /* Override settings per board. */
550 }
551
552 static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
553 const struct soc_intel_alderlake_config *config)
554 {
555 for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
556 s_cfg->SerialIoI2cMode[i] = config->serial_io_i2c_mode[i];
557
558 for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
559 s_cfg->SerialIoSpiMode[i] = config->serial_io_gspi_mode[i];
560 s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i];
561 s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i];
562 }
563
564 for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
565 s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i];
566 }
567
568 static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg,
569 const struct soc_intel_alderlake_config *config)
570 {
571 const struct microcode *microcode_file;
572 size_t microcode_len;
573
574 /* Locate microcode and pass to FSP-S for 2nd microcode loading */
575 microcode_file = intel_microcode_find();
576
577 if (microcode_file != NULL) {
578 microcode_len = get_microcode_size(microcode_file);
579 if (microcode_len != 0) {
580 /* Update CPU Microcode patch base address/size */
581 s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file;
582 s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len;
583 }
584 }
585 }
586
587 static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
588 const struct soc_intel_alderlake_config *config)
589 {
590 /*
591 * FIXME: FSP assumes ownership of the APs (Application Processors)
592 * upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD.
593 * Hence, pass a valid pointer to the CpuMpPpi UPD unconditionally.
594 * This would avoid APs from getting hijacked by FSP while coreboot
595 * decides to set SkipMpInit UPD.
596 */
597 s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
598
599 if (CONFIG(USE_FSP_MP_INIT))
600 /*
601 * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature
602 * programming.
603 */
604 fill_fsps_microcode_params(s_cfg, config);
605 else
606 s_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
607 }
608
609 static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
610 const struct soc_intel_alderlake_config *config)
611 {
612 /* Load VBT before devicetree-specific config. */
613 s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get();
614
615 /* Check if IGD is present and fill Graphics init param accordingly */
616 s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
617 s_cfg->LidStatus = CONFIG(RUN_FSP_GOP);
618 s_cfg->PavpEnable = CONFIG(PAVP);
619 }
620
621 WEAK_DEV_PTR(tcss_usb3_port1);
622 WEAK_DEV_PTR(tcss_usb3_port2);
623 WEAK_DEV_PTR(tcss_usb3_port3);
624 WEAK_DEV_PTR(tcss_usb3_port4);
625
626 static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
627 const struct soc_intel_alderlake_config *config)
628 {
629 const struct device *tcss_port_arr[] = {
630 DEV_PTR(tcss_usb3_port1),
631 DEV_PTR(tcss_usb3_port2),
632 DEV_PTR(tcss_usb3_port3),
633 DEV_PTR(tcss_usb3_port4),
634 };
635
636 s_cfg->TcssAuxOri = config->tcss_aux_ori;
637
638 /* Explicitly clear this field to avoid using defaults */
639 memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
640
641 /*
642 * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
643 * evaluate this UPD value and skip sending command. There will be no
644 * delay for command completion.
645 */
646 s_cfg->ITbtConnectTopologyTimeoutInMs = 0;
647
648 /* D3Hot and D3Cold for TCSS */
649 s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
650 s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable;
651
652 s_cfg->UsbTcPortEn = 0;
653 for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
654 if (is_dev_enabled(tcss_port_arr[i]))
655 s_cfg->UsbTcPortEn |= BIT(i);
656 }
657 }
658
659 static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
660 const struct soc_intel_alderlake_config *config)
661 {
662 /* Chipset Lockdown */
663 const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
664 s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp;
665 s_cfg->PchLockDownBiosInterface = lockdown_by_fsp;
666 s_cfg->PchUnlockGpioPads = lockdown_by_fsp;
667 s_cfg->RtcMemoryLock = lockdown_by_fsp;
668 s_cfg->SkipPamLock = !lockdown_by_fsp;
669
670 /* coreboot will send EOP before loading payload */
671 s_cfg->EndOfPostMessage = EOP_DISABLE;
672 }
673
674 static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
675 const struct soc_intel_alderlake_config *config)
676 {
677 int i;
678 /* USB */
679 for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
680 s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable;
681 s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
682 s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
683 s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
684 s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
685
686 if (config->usb2_ports[i].enable)
687 s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
688 else
689 s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
690
691 if (config->usb2_ports[i].type_c)
692 s_cfg->PortResetMessageEnable[i] = 1;
693 }
694
695 for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
696 s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable;
697 if (config->usb3_ports[i].enable)
698 s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
699 else
700 s_cfg->Usb3OverCurrentPin[i] = OC_SKIP;
701
702 if (config->usb3_ports[i].tx_de_emp) {
703 s_cfg->Usb3HsioTxDeEmphEnable[i] = 1;
704 s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
705 }
706 if (config->usb3_ports[i].tx_downscale_amp) {
707 s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1;
708 s_cfg->Usb3HsioTxDownscaleAmp[i] =
709 config->usb3_ports[i].tx_downscale_amp;
710 }
711 }
712
713 for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
714 if (config->tcss_ports[i].enable)
715 s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
716 }
717
718 s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable;
719 }
720
721 static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
722 const struct soc_intel_alderlake_config *config)
723 {
724 s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
725 }
726
727 static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,
728 const struct soc_intel_alderlake_config *config)
729 {
730 if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) &&
731 CONFIG(FSP_ENABLE_SERIAL_DEBUG))
732 s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
733 fsp_debug_event_handler);
734 /* PCH UART selection for FSP Debug */
735 s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
736 ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
737 s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
738 }
739
740 static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
741 const struct soc_intel_alderlake_config *config)
742 {
743 /* SATA */
744 s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
745 if (s_cfg->SataEnable) {
746 s_cfg->SataMode = config->sata_mode;
747 s_cfg->SataSalpSupport = config->sata_salp_support;
748 memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable,
749 sizeof(s_cfg->SataPortsEnable));
750 memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp,
751 sizeof(s_cfg->SataPortsDevSlp));
752 }
753
754 /*
755 * Power Optimizer for SATA.
756 * SataPwrOptimizeDisable is default to 0.
757 * Boards not needing the optimizers explicitly disables them by setting
758 * these disable variables to 1 in devicetree overrides.
759 */
760 s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable);
761 /* Test mode for SATA margining */
762 s_cfg->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE);
763 /*
764 * Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
765 * SataPortsDmVal is the DITO multiplier. Default is 15.
766 * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
767 * The default values can be changed from devicetree.
768 */
769 for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) {
770 if (config->sata_ports_enable_dito_config[i]) {
771 s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i];
772 s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i];
773 }
774 }
775 }
776
777 static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg,
778 const struct soc_intel_alderlake_config *config)
779 {
780 /* Enable TCPU for processor thermal control */
781 s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
782
783 /* Set TccActivationOffset */
784 s_cfg->TccActivationOffset = config->tcc_offset;
785 }
786
787 static void fill_fsps_gna_params(FSP_S_CONFIG *s_cfg,
788 const struct soc_intel_alderlake_config *config)
789 {
790 s_cfg->GnaEnable = is_devfn_enabled(SA_DEVFN_GNA);
791 }
792
793 static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg,
794 const struct soc_intel_alderlake_config *config)
795 {
796 /* LAN */
797 s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
798 }
799
800 static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
801 const struct soc_intel_alderlake_config *config)
802 {
803 /* CNVi */
804 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
805 #if !CONFIG(SOC_INTEL_RAPTORLAKE)
806 /* This option is only available in public FSP headers of ADL-P and ADL-S */
807 s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
808 #endif
809 #endif
810 s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
811 s_cfg->CnviBtCore = config->cnvi_bt_core;
812 s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload;
813 /* Assert if CNVi BT is enabled without CNVi being enabled. */
814 assert(s_cfg->CnviMode || !s_cfg->CnviBtCore);
815 /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */
816 assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload);
817 }
818
819 static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg,
820 const struct soc_intel_alderlake_config *config)
821 {
822 /* VMD */
823 s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD);
824 }
825
826 static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg,
827 const struct soc_intel_alderlake_config *config)
828 {
829 /* THC */
830 s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE;
831 s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
832 }
833
834 static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg,
835 const struct soc_intel_alderlake_config *config)
836 {
837 /* USB4/TBT */
838 for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++)
839 s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i));
840 }
841
842 static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
843 const struct soc_intel_alderlake_config *config)
844 {
845 /* Legacy 8254 timer support */
846 bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
847 s_cfg->Enable8254ClockGating = !use_8254;
848 s_cfg->Enable8254ClockGatingOnS3 = !use_8254;
849 }
850
851 static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg,
852 const struct soc_intel_alderlake_config *config)
853 {
854 /*
855 * Legacy PM ACPI Timer (and TCO Timer)
856 * This *must* be 1 in any case to keep FSP from
857 * 1) enabling PM ACPI Timer emulation in uCode.
858 * 2) disabling the PM ACPI Timer.
859 * We handle both by ourself!
860 */
861 s_cfg->EnableTcoTimer = 1;
862 }
863
864 static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg,
865 const struct soc_intel_alderlake_config *config)
866 {
867 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
868 /* eMMC Configuration */
869 s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
870 if (s_cfg->ScsEmmcEnabled)
871 s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode;
872 #endif
873
874 /* UFS Configuration */
875 s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */
876 s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS);
877
878 /* Enable Hybrid storage auto detection */
879 s_cfg->HybridStorageMode = config->hybrid_storage_mode;
880 }
881
882 static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
883 const struct soc_intel_alderlake_config *config)
884 {
885 uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
886 for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) {
887 if (!(enable_mask & BIT(i)))
888 continue;
889 const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i];
890 s_cfg->PcieRpL1Substates[i] =
891 get_l1_substate_control(rp_cfg->PcieRpL1Substates);
892 s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
893 s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
894 s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
895 || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
896 s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
897 if (rp_cfg->pcie_rp_aspm)
898 s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
899 /* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */
900 if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
901 s_cfg->PcieRpSlotImplemented[i] = 0;
902 s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
903 }
904 s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
905 }
906
907 static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg,
908 const struct soc_intel_alderlake_config *config)
909 {
910 if (!CONFIG_MAX_CPU_ROOT_PORTS)
911 return;
912
913 const uint32_t enable_mask = pcie_rp_enable_mask(get_cpu_pcie_rp_table());
914 for (int i = 0; i < CONFIG_MAX_CPU_ROOT_PORTS; i++) {
915 if (!(enable_mask & BIT(i)))
916 continue;
917
918 const struct pcie_rp_config *rp_cfg = &config->cpu_pcie_rp[i];
919 s_cfg->CpuPcieRpL1Substates[i] =
920 get_l1_substate_control(rp_cfg->PcieRpL1Substates);
921 s_cfg->CpuPcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
922 s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
923 s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
924 || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
925 s_cfg->CpuPcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
926 s_cfg->PtmEnabled[i] = 0;
927 if (rp_cfg->pcie_rp_aspm)
928 s_cfg->CpuPcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
929
930 if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
931 s_cfg->CpuPcieRpSlotImplemented[i] = 0;
932 }
933 s_cfg->CpuPcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
934 }
935
936 static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
937 const struct soc_intel_alderlake_config *config)
938 {
939 /* Skip setting D0I3 bit for all HECI devices */
940 s_cfg->DisableD0I3SettingForHeci = 1;
941 /*
942 * Power Optimizer for DMI
943 * DmiPwrOptimizeDisable is default to 0.
944 * Boards not needing the optimizers explicitly disables them by setting
945 * these disable variables to 1 in devicetree overrides.
946 */
947 s_cfg->PchPwrOptEnable = !(config->dmi_power_optimize_disable);
948 s_cfg->PmSupport = 1;
949 s_cfg->Hwp = 1;
950 s_cfg->Cx = 1;
951 s_cfg->PsOnEnable = 1;
952 s_cfg->PkgCStateLimit = LIMIT_AUTO;
953
954 /* Disable Energy Efficient Turbo mode */
955 s_cfg->EnergyEfficientTurbo = 0;
956
957 /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */
958 s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS;
959
960 /* VrConfig Settings for IA and GT domains */
961 for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
962 fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]);
963
964 s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
965
966 /* Apply minimum assertion width settings */
967 if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT)
968 s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS;
969 else
970 s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width;
971
972 if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT)
973 s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S;
974 else
975 s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width;
976
977 if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT)
978 s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S;
979 else
980 s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width;
981
982 if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT)
983 s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S;
984 else
985 s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width;
986
987 unsigned int power_cycle_duration = config->pch_reset_power_cycle_duration;
988 if (power_cycle_duration == POWER_CYCLE_DURATION_DEFAULT)
989 power_cycle_duration = POWER_CYCLE_DURATION_4S;
990
991 s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert,
992 s_cfg->PchPmSlpS3MinAssert,
993 s_cfg->PchPmSlpAMinAssert,
994 power_cycle_duration);
995
996 /* Set PsysPmax if it is available from DT */
997 if (config->platform_pmax) {
998 printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->platform_pmax);
999 /* PsysPmax is in unit of 1/8 Watt */
1000 s_cfg->PsysPmax = config->platform_pmax * 8;
1001 }
1002
1003 s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion;
1004
1005 s_cfg->VrPowerDeliveryDesign = config->vr_power_delivery_design;
1006
1007 s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion;
1008 }
1009
1010 static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
1011 const struct soc_intel_alderlake_config *config)
1012 {
1013 const struct slot_irq_constraints *constraints;
1014 size_t num_slots;
1015
1016 if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) {
1017 constraints = irq_constraints_pch_s;
1018 num_slots = ARRAY_SIZE(irq_constraints_pch_s);
1019 } else {
1020 constraints = irq_constraints;
1021 num_slots = ARRAY_SIZE(irq_constraints);
1022 }
1023
1024 if (!assign_pci_irqs(constraints, num_slots))
1025 die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n");
1026
1027 size_t pch_count = 0;
1028 const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
1029
1030 s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
1031 s_cfg->NumOfDevIntConfig = pch_count;
1032 printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
1033 }
1034
1035 static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
1036 const struct soc_intel_alderlake_config *config)
1037 {
1038 /* PCH FIVR settings override */
1039 if (!config->ext_fivr_settings.configure_ext_fivr)
1040 return;
1041
1042 s_cfg->PchFivrExtV1p05RailEnabledStates =
1043 config->ext_fivr_settings.v1p05_enable_bitmap;
1044
1045 s_cfg->PchFivrExtV1p05RailSupportedVoltageStates =
1046 config->ext_fivr_settings.v1p05_supported_voltage_bitmap;
1047
1048 s_cfg->PchFivrExtVnnRailEnabledStates =
1049 config->ext_fivr_settings.vnn_enable_bitmap;
1050
1051 s_cfg->PchFivrExtVnnRailSupportedVoltageStates =
1052 config->ext_fivr_settings.vnn_supported_voltage_bitmap;
1053
1054 s_cfg->PchFivrExtVnnRailSxEnabledStates =
1055 config->ext_fivr_settings.vnn_sx_enable_bitmap;
1056
1057 /* Convert the voltages to increments of 2.5mv */
1058 s_cfg->PchFivrExtV1p05RailVoltage =
1059 (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25;
1060
1061 s_cfg->PchFivrExtVnnRailVoltage =
1062 (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25;
1063
1064 s_cfg->PchFivrExtVnnRailSxVoltage =
1065 (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25);
1066
1067 s_cfg->PchFivrExtV1p05RailIccMaximum =
1068 config->ext_fivr_settings.v1p05_icc_max_ma;
1069
1070 s_cfg->PchFivrExtVnnRailIccMaximum =
1071 config->ext_fivr_settings.vnn_icc_max_ma;
1072
1073 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
1074 /* Enable the FIVR VCCST ICCMax Control for ADL-N.
1075 * TODO:Right now the UPD is update in partial headers for only ADL-N and when its
1076 * updated for ADL-P then we will remove the config since this needs to be enabled for
1077 * all the Alderlake platforms.
1078 */
1079 s_cfg->PchFivrVccstIccMaxControl = 1;
1080 #endif
1081 }
1082
1083 static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,
1084 const struct soc_intel_alderlake_config *config)
1085 {
1086 /* transform from Hz to 100 KHz */
1087 s_cfg->FivrRfiFrequency = config->fivr_rfi_frequency / (100 * KHz);
1088 s_cfg->FivrSpreadSpectrum = config->fivr_spread_spectrum;
1089 }
1090
1091 static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg,
1092 const struct soc_intel_alderlake_config *config)
1093 {
1094 s_cfg->AcousticNoiseMitigation = config->acoustic_noise_mitigation;
1095
1096 if (s_cfg->AcousticNoiseMitigation) {
1097 s_cfg->PreWake = config->PreWake;
1098 for (int i = 0; i < NUM_VR_DOMAINS; i++) {
1099 s_cfg->FastPkgCRampDisable[i] = config->fast_pkg_c_ramp_disable[i];
1100 s_cfg->SlowSlewRate[i] = config->slow_slew_rate[i];
1101 }
1102 }
1103 }
1104
1105 static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg,
1106 const struct soc_intel_alderlake_config *config)
1107 {
1108 struct device *dev;
1109 int i;
1110 /*
1111 * Prevent FSP from programming write-once subsystem IDs by providing
1112 * a custom SSID table. Must have at least one entry for the FSP to
1113 * use the table.
1114 */
1115 struct svid_ssid_init_entry {
1116 union {
1117 struct {
1118 uint64_t reg:12; /* Register offset */
1119 uint64_t function:3;
1120 uint64_t device:5;
1121 uint64_t bus:8;
1122 uint64_t :4;
1123 uint64_t segment:16;
1124 uint64_t :16;
1125 };
1126 uint64_t segbusdevfuncregister;
1127 };
1128 struct {
1129 uint16_t svid;
1130 uint16_t ssid;
1131 };
1132 uint32_t reserved;
1133 };
1134
1135 /*
1136 * The xHCI and HDA devices have RW/L rather than RW/O registers for
1137 * subsystem IDs and so must be written before FspSiliconInit locks
1138 * them with their default values.
1139 */
1140 const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA };
1141 static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)];
1142
1143 for (i = 0; i < ARRAY_SIZE(devfn_table); i++) {
1144 ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID;
1145 ssid_table[i].device = PCI_SLOT(devfn_table[i]);
1146 ssid_table[i].function = PCI_FUNC(devfn_table[i]);
1147 dev = pcidev_path_on_root(devfn_table[i]);
1148 if (dev) {
1149 ssid_table[i].svid = dev->subsystem_vendor;
1150 ssid_table[i].ssid = dev->subsystem_device;
1151 }
1152 }
1153
1154 s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table;
1155 s_cfg->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
1156
1157 /*
1158 * Replace the default SVID:SSID value with the values specified in
1159 * the devicetree for the root device.
1160 */
1161 dev = pcidev_path_on_root(SA_DEVFN_ROOT);
1162 s_cfg->SiCustomizedSvid = dev->subsystem_vendor;
1163 s_cfg->SiCustomizedSsid = dev->subsystem_device;
1164
1165 /* Ensure FSP will program the registers */
1166 s_cfg->SiSkipSsidProgramming = 0;
1167 }
1168
1169 static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
1170 struct soc_intel_alderlake_config *config)
1171 {
1172 /* Override settings per board if required. */
1173 mainboard_update_soc_chip_config(config);
1174
1175 void (*const fill_fsps_params[])(FSP_S_CONFIG *s_cfg,
1176 const struct soc_intel_alderlake_config *config) = {
1177 fill_fsps_lpss_params,
1178 fill_fsps_cpu_params,
1179 fill_fsps_igd_params,
1180 fill_fsps_tcss_params,
1181 fill_fsps_chipset_lockdown_params,
1182 fill_fsps_xhci_params,
1183 fill_fsps_xdci_params,
1184 fill_fsps_uart_params,
1185 fill_fsps_sata_params,
1186 fill_fsps_thermal_params,
1187 fill_fsps_gna_params,
1188 fill_fsps_lan_params,
1189 fill_fsps_cnvi_params,
1190 fill_fsps_vmd_params,
1191 fill_fsps_thc_params,
1192 fill_fsps_tbt_params,
1193 fill_fsps_8254_params,
1194 fill_fsps_pm_timer_params,
1195 fill_fsps_storage_params,
1196 fill_fsps_pcie_params,
1197 fill_fsps_cpu_pcie_params,
1198 fill_fsps_misc_power_params,
1199 fill_fsps_irq_params,
1200 fill_fsps_fivr_params,
1201 fill_fsps_fivr_rfi_params,
1202 fill_fsps_acoustic_params,
1203 fill_fsps_pci_ssid_params,
1204 };
1205
1206 for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)
1207 fill_fsps_params[i](s_cfg, config);
1208 }
1209
1210 /* UPD parameters to be initialized before SiliconInit */
1211 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
1212 {
1213 struct soc_intel_alderlake_config *config;
1214 FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
1215
1216 config = config_of_soc();
1217 soc_silicon_init_params(s_cfg, config);
1218 mainboard_silicon_init_params(s_cfg);
1219 }
1220
1221 /*
1222 * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
1223 * This platform supports below MultiPhaseSIInit Phase(s):
1224 * Phase | FSP return point | Purpose
1225 * ------- + ------------------------------------------------ + -------------------------------
1226 * 1 | After TCSS initialization completed | for TCSS specific init
1227 * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init
1228 */
1229 void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
1230 {
1231 switch (phase_index) {
1232 case 1:
1233 /* TCSS specific initialization here */
1234 printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
1235 __FILE__, __func__);
1236
1237 if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
1238 const config_t *config = config_of_soc();
1239 tcss_configure(config->typec_aux_bias_pads);
1240 }
1241 break;
1242 case 2:
1243 /* CPU specific initialization here */
1244 printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
1245 __FILE__, __func__);
1246 before_post_cpus_init();
1247 /* Enable BIOS Reset CPL */
1248 enable_bios_reset_cpl();
1249 break;
1250 default:
1251 break;
1252 }
1253 }
1254
1255 /* Mainboard GPIO Configuration */
1256 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
1257 {
1258 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
1259 }
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