src/soc/intel/alderlake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Alder Lake Processor SA Datasheet
   5  * Document number: 619503
   6  * Chapter number: 3
   7  */
   8
   9 #include <arch/ioapic.h>
  10 #include <console/console.h>
  11 #include <cpu/x86/msr.h>
  12 #include <device/device.h>
  13 #include <device/pci.h>
  14 #include <delay.h>
  15 #include <intelblocks/cpulib.h>
  16 #include <intelblocks/msr.h>
  17 #include <intelblocks/power_limit.h>
  18 #include <intelblocks/systemagent.h>
  19 #include <soc/iomap.h>
  20 #include <soc/soc_chip.h>
  21 #include <soc/systemagent.h>
  22 #include <spi_flash.h>
  23 #include "stddef.h"
  24
  25 /*
  26  * SoC implementation
  27  *
  28  * Add all known fixed memory ranges for Host Controller/Memory
  29  * controller.
  30  */
  31 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  32 {
  33         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  34                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  35                 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
  36                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  37                 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
  38                 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
  39
  40                 /* first field (sa_mmio_descriptor.index) is not used, setting to 0: */
  41                 { 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" },
  42                 { 0, TPM_BASE_ADDRESS, TPM_SIZE, "TPM" },
  43                 { 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" },
  44                 { 0, IO_APIC_ADDR, APIC_SIZE, "APIC" },
  45                 // PCH_PRESERVERD covers:
  46                 // TraceHub SW BAR, SBREG, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode
  47                 // eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR
  48                 // see fsp/ClientOneSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
  49                 { 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" },
  50         };
  51
  52         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  53                         ARRAY_SIZE(soc_fixed_resources));
  54
  55         /* Add Vt-d resources if VT-d is enabled */
  56         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  57                 return;
  58
  59         sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
  60                         ARRAY_SIZE(soc_vtd_resources));
  61 }
  62
  63 /*
  64  * set MMIO resource's fields
  65  */
  66 static void set_mmio_resource(
  67         struct sa_mmio_descriptor *resource,
  68         uint64_t base,
  69         uint64_t size,
  70         const char *description)
  71 {
  72         if (resource == NULL) {
  73                 printk(BIOS_ERR, "%s: argument resource is NULL for %s\n",
  74                 __func__, description);
  75                 return;
  76         }
  77         resource->base = base;
  78         resource->size = size;
  79         resource->description = description;
  80 }
  81
  82 int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
  83         uint64_t *prmrr_mask)
  84 {
  85         msr_t msr;
  86         msr = rdmsr(MSR_PRMRR_BASE_0);
  87         *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
  88         msr = rdmsr(MSR_PRMRR_PHYS_MASK);
  89         *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
  90         return 0;
  91 }
  92
  93 /*
  94  * SoC implementation
  95  *
  96  * Add all known configurable memory ranges for Host Controller/Memory
  97  * controller.
  98  */
  99 void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
 100 {
 101         uint64_t size, base, tseg_base;
 102         int count = 0;
 103         struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */
 104
 105         /* MMCONF */
 106         size = get_mmcfg_size(dev);
 107         if (size > 0)
 108                 set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS,
 109                         size, "MMCONF");
 110
 111         /* DSM */
 112         size = get_dsm_size(dev);
 113         if (size > 0) {
 114                 base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000;
 115                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
 116         }
 117
 118         /* TSEG */
 119         size = sa_get_tseg_size();
 120         tseg_base = sa_get_tseg_base();
 121         if (size > 0)
 122                 set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");
 123
 124         /* PMRR */
 125         size = get_valid_prmrr_size();
 126         if (size > 0) {
 127                 uint64_t mask;
 128                 if (soc_get_uncore_prmmr_base_and_mask(&base, &mask) == 0) {
 129                         base &= mask;
 130                         set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR");
 131                 } else {
 132                         printk(BIOS_ERR, "SA: Failed to get PRMRR base and mask\n");
 133                 }
 134         }
 135
 136         /* GSM */
 137         size = get_gsm_size(dev);
 138         if (size > 0) {
 139                 base = sa_get_gsm_base();
 140                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM");
 141         }
 142
 143         /* DPR */
 144         size = get_dpr_size(dev);
 145         if (size > 0) {
 146                 /* DPR just below TSEG: */
 147                 base = tseg_base - size;
 148                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DPR");
 149         }
 150
 151         /* Add all the above */
 152         sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count);
 153 }
 154
 155 /*
 156  * SoC implementation
 157  *
 158  * Perform System Agent Initialization during Ramstage phase.
 159  */
 160 void soc_systemagent_init(struct device *dev)
 161 {
 162         struct soc_power_limits_config *soc_config;
 163         struct device *sa;
 164         uint16_t sa_pci_id;
 165         u8 tdp;
 166         size_t i;
 167         config_t *config;
 168
 169         /* Enable Power Aware Interrupt Routing */
 170         enable_power_aware_intr();
 171
 172         config = config_of_soc();
 173
 174         /* Get System Agent PCI ID */
 175         sa = pcidev_path_on_root(SA_DEVFN_ROOT);
 176         sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
 177
 178         tdp = get_cpu_tdp();
 179
 180         /* Choose power limits configuration based on the CPU SA PCI ID and
 181          * CPU TDP value. */
 182         for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
 183                 if (sa_pci_id == cpuid_to_adl[i].cpu_id &&
 184                                 tdp == cpuid_to_adl[i].cpu_tdp) {
 185                         soc_config = &config->power_limits_config[cpuid_to_adl[i].limits];
 186                         set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 187                         break;
 188                 }
 189         }
 190
 191         if (i == ARRAY_SIZE(cpuid_to_adl)) {
 192                 printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipped power limits configuration.\n",
 193                         sa_pci_id);
 194                 return;
 195         }
 196 }
 197
 198 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
 199 {
 200         switch (capid0_a_ddrsz) {
 201         case 1:
 202                 return 8192;
 203         case 2:
 204                 return 4096;
 205         case 3:
 206                 return 2048;
 207         default:
 208                 return 65536;
 209         }
 210 }
 211
 212 uint64_t get_mmcfg_size(const struct device *dev)
 213 {
 214         uint32_t pciexbar_reg;
 215         uint64_t mmcfg_length;
 216
 217         if (!dev) {
 218                 printk(BIOS_DEBUG, "%s : device is null\n", __func__);
 219                 return 0;
 220         }
 221
 222         pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
 223
 224         if (!(pciexbar_reg & (1 << 0))) {
 225                 printk(BIOS_DEBUG, "%s : PCIEXBAR disabled\n", __func__);
 226                 return 0;
 227         }
 228
 229         switch ((pciexbar_reg & MASK_PCIEXBAR_LENGTH) >> PCIEXBAR_LENGTH_LSB) {
 230         case PCIEXBAR_LENGTH_4096MB:
 231                 mmcfg_length = 4 * ((uint64_t)GiB);
 232                 break;
 233         case PCIEXBAR_LENGTH_2048MB:
 234                 mmcfg_length = 2 * ((uint64_t)GiB);
 235                 break;
 236         case PCIEXBAR_LENGTH_1024MB:
 237                 mmcfg_length = 1 * GiB;
 238                 break;
 239         case PCIEXBAR_LENGTH_512MB:
 240                 mmcfg_length = 512 * MiB;
 241                 break;
 242         case PCIEXBAR_LENGTH_256MB:
 243                 mmcfg_length = 256 * MiB;
 244                 break;
 245         case PCIEXBAR_LENGTH_128MB:
 246                 mmcfg_length = 128 * MiB;
 247                 break;
 248         case PCIEXBAR_LENGTH_64MB:
 249                 mmcfg_length = 64 * MiB;
 250                 break;
 251         default:
 252                 printk(BIOS_DEBUG, "%s : PCIEXBAR - invalid length (0x%x)\n", __func__,
 253                         pciexbar_reg & MASK_PCIEXBAR_LENGTH);
 254                 mmcfg_length = 0x0;
 255                 break;
 256         }
 257
 258         return mmcfg_length;
 259 }
 260
 261 uint64_t get_dsm_size(const struct device *dev)
 262 {
 263         // - size : B0/D0/F0:R 50h [15:8]
 264         uint32_t reg32 = pci_read_config32(dev, GGC);
 265         uint64_t size;
 266         uint32_t size_field = (reg32 & MASK_DSM_LENGTH) >> MASK_DSM_LENGTH_LSB;
 267         if (size_field <= 0x10) { // 0x0 - 0x10
 268                 size = size_field * 32 * MiB;
 269         } else if ((size_field >= 0xF0) && (size_field >= 0xFE)) {
 270                 size = ((uint64_t)size_field - 0xEF) * 4 * MiB;
 271         } else {
 272                 switch (size_field) {
 273                 case 0x20:
 274                         size = 1 * GiB;
 275                         break;
 276                 case 0x30:
 277                         size = 1536 * MiB;
 278                         break;
 279                 case 0x40:
 280                         size = 2 * (uint64_t)GiB;
 281                         break;
 282                 default:
 283                         printk(BIOS_DEBUG, "%s : DSM - invalid length (0x%x)\n",
 284                                 __func__, size_field);
 285                         size = 0x0;
 286                         break;
 287                 }
 288         }
 289         return size;
 290 }
 291
 292 uint64_t get_gsm_size(const struct device *dev)
 293 {
 294         const u32 gsm_size = pci_read_config32(dev, GGC);
 295         uint64_t size;
 296         uint32_t size_field = (gsm_size & MASK_GSM_LENGTH) >> MASK_GSM_LENGTH_LSB;
 297         switch (size_field) {
 298         case 0x0:
 299                 size = 0;
 300                 break;
 301         case 0x1:
 302                 size = 2 * MiB;
 303                 break;
 304         case 0x2:
 305                 size = 4 * MiB;
 306                 break;
 307         case 0x3:
 308                 size = 8 * MiB;
 309                 break;
 310         default:
 311                 size = 0;
 312                 break;
 313         }
 314         return size;
 315 }
 316 uint64_t get_dpr_size(const struct device *dev)
 317 {
 318         uint64_t size;
 319         uint32_t dpr_reg = pci_read_config32(dev, DPR_REG);
 320         uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB;
 321         size = (uint64_t)size_field * MiB;
 322         return size;
 323 }