src/soc/intel/alderlake/vr_config.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pci_ids.h>
   4 #include <device/pci_ops.h>
   5 #include <fsp/api.h>
   6 #include <soc/ramstage.h>
   7 #include <soc/vr_config.h>
   8 #include <console/console.h>
   9 #include <intelblocks/cpulib.h>
  10
  11 /*
  12  * VR Configurations for IA and GT domains for ADL-P SKU's.
  13  * Per doc#627345 ADL_P Partial Intel PlatformDesignStudio Rev 2.0.0, update PD
  14  *
  15  * +----------------+-----------+-------+-------+---------+-------------+----------+
  16  * |      SKU       | Setting   | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
  17  * |                |           |(mOhms)|(mOhms)|   (A)   |     (A)     |   (msec) |
  18  * +----------------+-----------+-------+-------+---------+-------------+----------+
  19  * | ADL-P 682(45W) |    IA     |  2.3  |  2.3  |   160   |      57     |  28000   |
  20  * +                +-----------+-------+-------+---------+-------------+----------+
  21  * |                |    GT     |  3.2  |  3.2  |    55   |      57     |  28000   |
  22  * +----------------+-----------+-------+-------+---------+-------------+----------+
  23  * | ADL-P 482(45W) |    IA     |  2.3  |  2.3  |   120   |      47     |  28000   |
  24  * +       442(45W) +-----------+-------+-------+---------+-------------+----------+
  25  * |                |    GT     |  3.2  |  3.2  |    55   |      47     |  28000   |
  26  * +----------------+-----------+-------+-------+---------+-------------+----------+
  27  * | ADL-P 682(28W) |    IA     |  2.3  |  2.3  |   109   |      40     |  28000   |
  28  * +                +-----------+-------+-------+---------+-------------+----------+
  29  * |                |    GT     |  3.2  |  3.2  |    55   |      40     |  28000   |
  30  * +----------------+-----------+-------+-------+---------+-------------+----------+
  31  * | ADL-P 482(28W) |    IA     |  2.3  |  2.3  |    85   |      32     |  28000   |
  32  * +                +-----------+-------+-------+---------+-------------+----------+
  33  * |                |    GT     |  3.2  |  3.2  |    55   |      32     |  28000   |
  34  * +----------------+-----------+-------+-------+---------+-------------+----------+
  35  * | ADL-P 282(15W) |    IA     |  2.8  |  2.8  |    80   |      20     |  28000   |
  36  * +                +-----------+-------+-------+---------+-------------+----------+
  37  * |                |    GT     |  3.2  |  3.2  |    40   |      20     |  28000   |
  38  * +----------------+-----------+-------+-------+---------+-------------+----------+
  39  */
  40
  41 /*
  42  * VR Configurations for IA and GT domains for ADL-N SKU's.
  43  * Per doc#646929 ADL N Platform Design Guide -> Power_Map_Rev1p0
  44  *
  45  * +----------------+-----------+-------+-------+---------+-------------+----------+
  46  * |      SKU       | Setting   | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
  47  * |                |           |(mOhms)|(mOhms)|   (A)   |     (A)     |   (msec) |
  48  * +----------------+-----------+-------+-------+---------+-------------+----------+
  49  * | ADL-N 081(15W) |    IA     |  4.7  |  4.7  |    53   |      22     |  28000   |
  50  * +                +-----------+-------+-------+---------+-------------+----------+
  51  * |                |    GT     |  6.5  |  6.5  |    29   |      22     |  28000   |
  52  * +----------------+-----------+-------+-------+---------+-------------+----------+
  53  * | ADL-N 081(7W)  |    IA     |  5.0  |  5.0  |    37   |      14     |  28000   |
  54  * +                +-----------+-------+-------+---------+-------------+----------+
  55  * |                |    GT     |  6.5  |  6.5  |    29   |      14     |  28000   |
  56  * +----------------+-----------+-------+-------+---------+-------------+----------+
  57  * | ADL-N 041(6W)  |    IA     |  5.0  |  5.0  |    37   |      12     |  28000   |
  58  * +  Pentium       +-----------+-------+-------+---------+-------------+----------+
  59  * |                |    GT     |  6.5  |  6.5  |    29   |      12     |  28000   |
  60  * +----------------+-----------+-------+-------+---------+-------------+----------+
  61  * | ADL-N 041(6W)  |    IA     |  5.0  |  5.0  |    37   |      12     |  28000   |
  62  * +  Celeron       +-----------+-------+-------+---------+-------------+----------+
  63  * |                |    GT     |  6.5  |  6.5  |    26   |      12     |  28000   |
  64  * +----------------+-----------+-------+-------+---------+-------------+----------+
  65  * | ADL-N 021(6W)  |    IA     |  5.0  |  5.0  |    27   |      10     |  28000   |
  66  * +                +-----------+-------+-------+---------+-------------+----------+
  67  * |                |    GT     |  6.5  |  6.5  |    23   |      10     |  28000   |
  68  * +----------------+-----------+-------+-------+---------+-------------+----------+
  69  */
  70
  71 /*
  72  * VR Configurations for IA and GT domains for RPL-P SKU's.
  73  * Per doc#686872 RPL UPH PDG - 2022, June 7th edition
  74  *
  75  * +----------------+-----------+-------+-------+---------+-------------+----------+
  76  * |      SKU       | Setting   | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
  77  * |                |           |(mOhms)|(mOhms)|   (A)   |     (A)     |   (msec) |
  78  * +----------------+-----------+-------+-------+---------+-------------+----------+
  79  * | RPL-P 682(45W) |    IA     |  2.3  |  2.3  |   160   |      86     |  28000   |
  80  * +                +-----------+-------+-------+---------+-------------+----------+
  81  * |                |    GT     |  3.2  |  3.2  |    55   |      86     |  28000   |
  82  * +----------------+-----------+-------+-------+---------+-------------+----------+
  83  * | RPL-P 482(28W) |    IA     |  2.3  |  2.3  |   102   |      54     |  28000   |
  84  * +                +-----------+-------+-------+---------+-------------+----------+
  85  * |                |    GT     |  3.2  |  3.2  |    55   |      54     |  28000   |
  86  * +----------------+-----------+-------+-------+---------+-------------+----------+
  87  * | RPL-P 282(15W) |    IA     |  2.8  |  2.8  |    80   |      41     |  28000   |
  88  * +                +-----------+-------+-------+---------+-------------+----------+
  89  * |                |    GT     |  3.2  |  3.2  |    40   |      41     |  28000   |
  90  * +----------------+-----------+-------+-------+---------+-------------+----------+
  91  */
  92
  93 struct vr_lookup {
  94         uint16_t mchid;
  95         uint8_t tdp;
  96         uint32_t conf[NUM_VR_DOMAINS];
  97 };
  98
  99 static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain,
 100                                         const uint16_t mch_id, uint8_t tdp)
 101 {
 102         for (size_t i = 0; i < tbl_entries; i++) {
 103                 if (tbl[i].mchid != mch_id || tbl[i].tdp != tdp)
 104                         continue;
 105                 return tbl[i].conf[domain];
 106         }
 107
 108         printk(BIOS_ERR, "Unknown MCH (0x%x) in %s\n", mch_id, __func__);
 109         return 0;
 110 }
 111
 112 /* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */
 113 static const struct vr_lookup vr_config_ll[] = {
 114         { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 115         { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 116         { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 117         { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 118         { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 119         { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 120         { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 121         { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
 122         { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
 123         { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
 124         { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) },
 125         { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 126         { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 127         { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 128         { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 129         { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 130         { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 131         { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
 132         { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
 133         { PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
 134         { PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
 135         { PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
 136         { PCI_DID_INTEL_ADL_S_ID_1,  35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 137         { PCI_DID_INTEL_ADL_S_ID_3,  125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
 138         { PCI_DID_INTEL_ADL_S_ID_3,  65,  VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
 139         { PCI_DID_INTEL_ADL_S_ID_3,  35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 140         { PCI_DID_INTEL_ADL_S_ID_8,  125, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 141         { PCI_DID_INTEL_ADL_S_ID_10, 65,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 142         { PCI_DID_INTEL_ADL_S_ID_10, 35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 143         { PCI_DID_INTEL_ADL_S_ID_11, 60,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 144         { PCI_DID_INTEL_ADL_S_ID_11, 58,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 145         { PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 146         { PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 147         { PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 148 };
 149
 150 static const struct vr_lookup vr_config_icc[] = {
 151         { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
 152         { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
 153         { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
 154         { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
 155         { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) },
 156         { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
 157         { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
 158         { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
 159         { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
 160         { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
 161         { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) },
 162         { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
 163         { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
 164         { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) },
 165         { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
 166         { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
 167         { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
 168         { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
 169         { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
 170         { PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
 171         { PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
 172         { PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_ICC(240, 30) },
 173         { PCI_DID_INTEL_ADL_S_ID_1,  35,  VR_CFG_ALL_DOMAINS_ICC(154, 30) },
 174         { PCI_DID_INTEL_ADL_S_ID_3,  125, VR_CFG_ALL_DOMAINS_ICC(240, 30) },
 175         { PCI_DID_INTEL_ADL_S_ID_3,  65,  VR_CFG_ALL_DOMAINS_ICC(220, 30) },
 176         { PCI_DID_INTEL_ADL_S_ID_3,  35,  VR_CFG_ALL_DOMAINS_ICC(145, 30) },
 177         { PCI_DID_INTEL_ADL_S_ID_8,  125, VR_CFG_ALL_DOMAINS_ICC(175, 30) },
 178         { PCI_DID_INTEL_ADL_S_ID_10, 65,  VR_CFG_ALL_DOMAINS_ICC(151, 30) },
 179         { PCI_DID_INTEL_ADL_S_ID_10, 35,  VR_CFG_ALL_DOMAINS_ICC(100, 30) },
 180         { PCI_DID_INTEL_ADL_S_ID_11, 60,  VR_CFG_ALL_DOMAINS_ICC(110, 30) },
 181         { PCI_DID_INTEL_ADL_S_ID_11, 58,  VR_CFG_ALL_DOMAINS_ICC(110, 30) },
 182         { PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_ICC(90, 30) },
 183         { PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_ICC(49, 30) },
 184         { PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_ICC(37, 30) },
 185 };
 186
 187 static const struct vr_lookup vr_config_tdc_timewindow[] = {
 188         { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 189         { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 190         { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 191         { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 192         { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 193         { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 194         { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 195         { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 196         { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 197         { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 198         { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 199         { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 200         { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 201         { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 202         { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 203         { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 204         { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 205         { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 206         { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 207         { PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 208         { PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 209         { PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 210         { PCI_DID_INTEL_ADL_S_ID_1,  35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 211         { PCI_DID_INTEL_ADL_S_ID_3,  125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 212         { PCI_DID_INTEL_ADL_S_ID_3,  65,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 213         { PCI_DID_INTEL_ADL_S_ID_3,  35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 214         { PCI_DID_INTEL_ADL_S_ID_8,  125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 215         { PCI_DID_INTEL_ADL_S_ID_10, 65,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 216         { PCI_DID_INTEL_ADL_S_ID_10, 35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 217         { PCI_DID_INTEL_ADL_S_ID_11, 60,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 218         { PCI_DID_INTEL_ADL_S_ID_11, 58,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 219         { PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 220         { PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 221         { PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 222 };
 223
 224 static const struct vr_lookup vr_config_tdc_currentlimit[] = {
 225         { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
 226         { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
 227         { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
 228         { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
 229         { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
 230         { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
 231         { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
 232         { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
 233         { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
 234         { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
 235         { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
 236         { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) },
 237         { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
 238         { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
 239         { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) },
 240         { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
 241         { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) },
 242         { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
 243         { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
 244         { PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
 245         { PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
 246         { PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
 247         { PCI_DID_INTEL_ADL_S_ID_1,  35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 56) },
 248         { PCI_DID_INTEL_ADL_S_ID_3,  125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(109, 109) },
 249         { PCI_DID_INTEL_ADL_S_ID_3,  65,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(77, 77) },
 250         { PCI_DID_INTEL_ADL_S_ID_3,  35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(49, 49) },
 251         { PCI_DID_INTEL_ADL_S_ID_8,  125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 96) },
 252         { PCI_DID_INTEL_ADL_S_ID_10, 65,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 66) },
 253         { PCI_DID_INTEL_ADL_S_ID_10, 35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 44) },
 254         { PCI_DID_INTEL_ADL_S_ID_11, 60,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 56) },
 255         { PCI_DID_INTEL_ADL_S_ID_11, 58,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(59, 59) },
 256         { PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
 257         { PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 39) },
 258         { PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 30) },
 259 };
 260
 261 static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg,
 262                 int domain, const struct vr_config *chip_cfg)
 263 {
 264 #if CONFIG(SOC_INTEL_RAPTORLAKE)
 265         s_cfg->EnableFastVmode[domain] = chip_cfg->enable_fast_vmode;
 266         if (s_cfg->EnableFastVmode[domain])
 267                 s_cfg->IccLimit[domain] = chip_cfg->fast_vmode_i_trip;
 268 #endif
 269 }
 270
 271 void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
 272                 int domain, const struct vr_config *chip_cfg)
 273 {
 274         const struct vr_config *cfg;
 275
 276         if (domain < 0 || domain >= NUM_VR_DOMAINS)
 277                 return;
 278
 279         /* Use device tree override if requested */
 280         if (chip_cfg->vr_config_enable) {
 281                 cfg = chip_cfg;
 282
 283                 if (cfg->ac_loadline)
 284                         s_cfg->AcLoadline[domain] = cfg->ac_loadline;
 285                 if (cfg->dc_loadline)
 286                         s_cfg->DcLoadline[domain] = cfg->dc_loadline;
 287                 if (cfg->icc_max)
 288                         s_cfg->IccMax[domain] = cfg->icc_max;
 289                 if (cfg->psi1threshold)
 290                         s_cfg->Psi1Threshold[domain] = cfg->psi1threshold;
 291                 if (cfg->psi2threshold)
 292                         s_cfg->Psi2Threshold[domain] = cfg->psi2threshold;
 293                 if (cfg->psi3threshold)
 294                         s_cfg->Psi3Threshold[domain] = cfg->psi3threshold;
 295                 s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow;
 296                 s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit;
 297         } else {
 298                 uint8_t tdp = get_cpu_tdp();
 299                 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 300                 uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
 301
 302                 s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll),
 303                                                         domain, mch_id, tdp);
 304                 s_cfg->DcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll),
 305                                                         domain, mch_id, tdp);
 306                 s_cfg->IccMax[domain] = load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc),
 307                                                         domain, mch_id, tdp);
 308                 s_cfg->TdcTimeWindow[domain] = load_table(vr_config_tdc_timewindow,
 309                                                         ARRAY_SIZE(vr_config_tdc_timewindow),
 310                                                         domain, mch_id, tdp);
 311                 s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit,
 312                                                         ARRAY_SIZE(vr_config_tdc_currentlimit),
 313                                                         domain, mch_id, tdp);
 314         }
 315
 316         fill_vr_fast_vmode(s_cfg, domain, chip_cfg);
 317
 318         /* Check TdcTimeWindow and TdcCurrentLimit,
 319            Set TdcEnable and Set VR TDC Input current to root mean square */
 320         if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) {
 321                 s_cfg->TdcEnable[domain] = 1;
 322                 s_cfg->Irms[domain] = 1;
 323         }
 324 }