src/mainboard/system76/kbl-u/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/skylake
   4         # Send an extra VR mailbox command for the PS4 exit issue
   5         register "SendVrMbxCmd" = "2"
   6
   7         # Power limit
   8         register "power_limits_config" = "{
   9                 .tdp_pl1_override = 20,
  10                 .tdp_pl2_override = 30,
  11         }"
  12
  13         # Enable Enhanced Intel SpeedStep
  14         register "eist_enable" = "true"
  15
  16         # Serial I/O
  17         register "SerialIoDevMode" = "{
  18                 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
  19         }"
  20
  21         # Power
  22         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  23         register "PmConfigSlpS4MinAssert" = "1"         # 1s
  24         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
  25         register "PmConfigSlpAMinAssert" = "3"          # 2s
  26
  27         # FSP Configuration
  28         register "SkipExtGfxScan" = "1"
  29         register "SaGv" = "SaGv_Enabled"
  30
  31         # VR Settings Configuration for 4 Domains
  32         #+----------------+-----------+-----------+-------------+----------+
  33         #| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
  34         #+----------------+-----------+-----------+-------------+----------+
  35         #| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
  36         #| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
  37         #| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
  38         #| Psi3Enable     | 1         | 1         | 1           | 1        |
  39         #| Psi4Enable     | 1         | 1         | 1           | 1        |
  40         #| ImonSlope      | 0         | 0         | 0           | 0        |
  41         #| ImonOffset     | 0         | 0         | 0           | 0        |
  42         #| IccMax         | 5A        | 64A       | 31A         | 31A      |
  43         #| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
  44         #+----------------+-----------+-----------+-------------+----------+
  45         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  46                 .vr_config_enable = 1,
  47                 .psi1threshold = VR_CFG_AMP(20),
  48                 .psi2threshold = VR_CFG_AMP(4),
  49                 .psi3threshold = VR_CFG_AMP(1),
  50                 .psi3enable = 0,
  51                 .psi4enable = 0,
  52                 .imon_slope = 0x0,
  53                 .imon_offset = 0x0,
  54                 .icc_max = VR_CFG_AMP(5),
  55                 .voltage_limit = 1520,
  56                 .ac_loadline = 1030,
  57                 .dc_loadline = 1030,
  58         }"
  59
  60         register "domain_vr_config[VR_IA_CORE]" = "{
  61                 .vr_config_enable = 1,
  62                 .psi1threshold = VR_CFG_AMP(20),
  63                 .psi2threshold = VR_CFG_AMP(5),
  64                 .psi3threshold = VR_CFG_AMP(1),
  65                 .psi3enable = 0,
  66                 .psi4enable = 0,
  67                 .imon_slope = 0x0,
  68                 .imon_offset = 0x0,
  69                 .icc_max = VR_CFG_AMP(64),
  70                 .voltage_limit = 1520,
  71                 .ac_loadline = 240,
  72                 .dc_loadline = 240,
  73         }"
  74
  75         register "domain_vr_config[VR_GT_UNSLICED]" = "{
  76                 .vr_config_enable = 1,
  77                 .psi1threshold = VR_CFG_AMP(20),
  78                 .psi2threshold = VR_CFG_AMP(5),
  79                 .psi3threshold = VR_CFG_AMP(1),
  80                 .psi3enable = 0,
  81                 .psi4enable = 0,
  82                 .imon_slope = 0x0,
  83                 .imon_offset = 0x0,
  84                 .icc_max = VR_CFG_AMP(31),
  85                 .voltage_limit = 1520,
  86                 .ac_loadline = 310,
  87                 .dc_loadline = 310,
  88         }"
  89
  90         register "domain_vr_config[VR_GT_SLICED]" = "{
  91                 .vr_config_enable = 1,
  92                 .psi1threshold = VR_CFG_AMP(20),
  93                 .psi2threshold = VR_CFG_AMP(5),
  94                 .psi3threshold = VR_CFG_AMP(1),
  95                 .psi3enable = 0,
  96                 .psi4enable = 0,
  97                 .imon_slope = 0x0,
  98                 .imon_offset = 0x0,
  99                 .icc_max = VR_CFG_AMP(31),
 100                 .voltage_limit = 1520,
 101                 .ac_loadline = 310,
 102                 .dc_loadline = 310,
 103         }"
 104
 105         device domain 0 on
 106                 device ref system_agent on end
 107                 device ref igpu on end
 108                 device ref sa_thermal on end
 109                 device ref south_xhci on
 110                         register "usb2_ports" = "{
 111                                 [0] = USB2_PORT_MID(OC_SKIP),           /* Type-A port right */
 112                                 [1] = USB2_PORT_FLEX(OC_SKIP),          /* 3G / LTE */
 113                                 [2] = USB2_PORT_TYPE_C(OC_SKIP),        /* Type-C port right */
 114                                 [3] = USB2_PORT_FLEX(OC_SKIP),          /* Camera */
 115                                 [4] = USB2_PORT_FLEX(OC_SKIP),          /* Bluetooth */
 116                                 [6] = USB2_PORT_FLEX(OC_SKIP),          /* Type-A port left */
 117                                 [7] = USB2_PORT_TYPE_C(OC_SKIP),        /* Type-C port right */
 118                         }"
 119                         register "usb3_ports" = "{
 120                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-A port right */
 121                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* 4G */
 122                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type C port right */
 123                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-A port left */
 124                         }"
 125                 end
 126                 device ref thermal on end
 127                 device ref sata on
 128                         register "SataSpeedLimit" = "2"
 129                         register "SataPortsEnable" = "{
 130                                 [0] = 1,
 131                                 [2] = 1,
 132                         }"
 133                 end
 134                 device ref pcie_rp1 on
 135                         # Root port #1 x4 (TBT)
 136                         register "PcieRpEnable[0]" = "1"
 137                         register "PcieRpClkReqSupport[0]" = "1"
 138                         register "PcieRpClkReqNumber[0]" = "4"
 139                         register "PcieRpClkSrcNumber[0]" = "4"
 140                         register "PcieRpAdvancedErrorReporting[0]" = "1"
 141                         register "PcieRpLtrEnable[0]" = "1"
 142                         register "PcieRpHotPlug[0]" = "1"
 143                 end
 144                 device ref pcie_rp5 on
 145                         # Root port #5 x1 (LAN)
 146                         register "PcieRpEnable[4]" = "1"
 147                         register "PcieRpClkReqSupport[4]" = "1"
 148                         register "PcieRpClkReqNumber[4]" = "3"
 149                         register "PcieRpClkSrcNumber[4]" = "3"
 150                         register "PcieRpAdvancedErrorReporting[4]" = "1"
 151                         register "PcieRpLtrEnable[4]" = "1"
 152                 end
 153                 device ref pcie_rp6 on
 154                         # Root port #6 x1 (WLAN)
 155                         register "PcieRpEnable[5]" = "1"
 156                         register "PcieRpClkReqSupport[5]" = "1"
 157                         register "PcieRpClkReqNumber[5]" = "2"
 158                         register "PcieRpClkSrcNumber[5]" = "2"
 159                         register "PcieRpAdvancedErrorReporting[5]" = "1"
 160                         register "PcieRpLtrEnable[5]" = "1"
 161                 end
 162                 device ref pcie_rp9 on
 163                         # Root port #9 x4 (NVMe)
 164                         register "PcieRpEnable[8]" = "1"
 165                         register "PcieRpClkReqSupport[8]" = "1"
 166                         register "PcieRpClkReqNumber[8]" = "5"
 167                         register "PcieRpClkSrcNumber[8]" = "5"
 168                         register "PcieRpAdvancedErrorReporting[8]" = "1"
 169                         register "PcieRpLtrEnable[8]" = "1"
 170                 end
 171                 device ref lpc_espi on
 172                         register "serirq_mode" = "SERIRQ_CONTINUOUS"
 173
 174                         register "gen1_dec" = "0x000c0681"
 175                         register "gen2_dec" = "0x000c1641"
 176                         register "gen3_dec" = "0x00040069"
 177                         chip drivers/pc80/tpm
 178                                 device pnp 0c31.0 on end
 179                         end
 180                 end
 181                 device ref p2sb off end
 182                 device ref pmc on
 183                         register "gpe0_dw0" = "GPP_C"
 184                         register "gpe0_dw1" = "GPP_D"
 185                         register "gpe0_dw2" = "GPP_E"
 186                 end
 187                 device ref hda on end
 188                 device ref smbus on end
 189                 device ref fast_spi on end
 190         end
 191 end