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MAINTAINERS: Clarify this is about active upstream development
[coreboot.git] / util / viatool / cpu.c
blobcd3b40d6053f502ab716fc651152e0a11d326f5f
1 /*
2 * inteltool - dump all registers on an Intel CPU + chipset based system.
3 *
4 * Copyright (C) 2008-2010 by coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <fcntl.h>
17 #include <unistd.h>
18 #include <stdio.h>
19 #include <stdlib.h>
20 #include <string.h>
21 #include <errno.h>
22
23 #include "viatool.h"
24
25 #ifdef __x86_64__
26 # define BREG "%%rbx"
27 #else
28 # define BREG "%%ebx"
29 #endif
30
31 int fd_msr;
32
33 unsigned int cpuid(unsigned int op)
34 {
35 uint32_t ret;
36
37 #if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__)
38 asm volatile (
39 "push " BREG "\n\t"
40 "cpuid\n\t"
41 "pop " BREG "\n\t"
42 : "=a" (ret) : "a" (op) : "%ecx", "%edx"
43 );
44 #else
45 asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx");
46 #endif
47
48 return ret;
49 }
50
51 #ifndef __DARWIN__
52 int msr_readerror = 0;
53
54 msr_t rdmsr(int addr)
55 {
56 uint32_t buf[2];
57 msr_t msr = { 0xffffffff, 0xffffffff };
58
59 if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
60 perror("Could not lseek() to MSR");
61 close(fd_msr);
62 exit(1);
63 }
64
65 if (read(fd_msr, buf, 8) == 8) {
66 msr.lo = buf[0];
67 msr.hi = buf[1];
68 return msr;
69 }
70
71 if (errno == 5) {
72 printf(" (*)"); // Not all bits of the MSR could be read
73 msr_readerror = 1;
74 } else {
75 // A severe error.
76 perror("Could not read() MSR");
77 close(fd_msr);
78 exit(1);
79 }
80
81 return msr;
82 }
83 #endif
84
85 int print_intel_core_msrs(void)
86 {
87 unsigned int i, core, id;
88 msr_t msr;
89
90 #define IA32_PLATFORM_ID 0x0017
91 #define EBL_CR_POWERON 0x002a
92 #define FSB_CLK_STS 0x00cd
93 #define IA32_TIME_STAMP_COUNTER 0x0010
94 #define IA32_APIC_BASE 0x001b
95
96 typedef struct {
97 int number;
98 char *name;
99 } msr_entry_t;
100
101 /* Pentium III */
102 static const msr_entry_t model67x_global_msrs[] = {
103 { 0x0000, "IA32_P5_MC_ADDR" },
104 { 0x0001, "IA32_P5_MC_TYPE" },
105 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
106 { 0x0017, "IA32_PLATFORM_ID" },
107 { 0x001b, "IA32_APIC_BASE" },
108 { 0x002a, "EBL_CR_POWERON" },
109 { 0x0033, "TEST_CTL" },
110 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
111 { 0x0088, "BBL_CR_D0" },
112 { 0x0089, "BBL_CR_D1" },
113 { 0x008a, "BBL_CR_D2" },
114 { 0x008b, "IA32_BIOS_SIGN_ID" },
115 { 0x00c1, "PERFCTR0" },
116 { 0x00c2, "PERFCTR1" },
117 { 0x00fe, "IA32_MTRRCAP" },
118 { 0x0116, "BBL_CR_ADDR" },
119 { 0x0118, "BBL_CR_DECC" },
120 { 0x0119, "BBL_CR_CTL" },
121 //{ 0x011a, "BBL_CR_TRIG" },
122 { 0x011b, "BBL_CR_BUSY" },
123 { 0x011e, "BBL_CR_CTL3" },
124 { 0x0174, "IA32_SYSENTER_CS" },
125 { 0x0175, "IA32_SYSENTER_ESP" },
126 { 0x0176, "IA32_SYSENTER_EIP" },
127 { 0x0179, "IA32_MCG_CAP" },
128 { 0x017a, "IA32_MCG_STATUS" },
129 { 0x017b, "IA32_MCG_CTL" },
130 { 0x0186, "IA32_PERF_EVNTSEL0" },
131 { 0x0187, "IA32_PERF_EVNTSEL1" },
132 { 0x01d9, "IA32_DEBUGCTL" },
133 { 0x01db, "MSR_LASTBRANCHFROMIP" },
134 { 0x01dc, "MSR_LASTBRANCHTOIP" },
135 { 0x01dd, "MSR_LASTINTFROMIP" },
136 { 0x01de, "MSR_LASTINTTOIP" },
137 { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" },
138 { 0x0200, "IA32_MTRR_PHYSBASE0" },
139 { 0x0201, "IA32_MTRR_PHYSMASK0" },
140 { 0x0202, "IA32_MTRR_PHYSBASE1" },
141 { 0x0203, "IA32_MTRR_PHYSMASK1" },
142 { 0x0204, "IA32_MTRR_PHYSBASE2" },
143 { 0x0205, "IA32_MTRR_PHYSMASK2" },
144 { 0x0206, "IA32_MTRR_PHYSBASE3" },
145 { 0x0207, "IA32_MTRR_PHYSMASK3" },
146 { 0x0208, "IA32_MTRR_PHYSBASE4" },
147 { 0x0209, "IA32_MTRR_PHYSMASK4" },
148 { 0x020a, "IA32_MTRR_PHYSBASE5" },
149 { 0x020b, "IA32_MTRR_PHYSMASK5" },
150 { 0x020c, "IA32_MTRR_PHYSBASE6" },
151 { 0x020d, "IA32_MTRR_PHYSMASK6" },
152 { 0x020e, "IA32_MTRR_PHYSBASE7" },
153 { 0x020f, "IA32_MTRR_PHYSMASK7" },
154 { 0x0250, "IA32_MTRR_FIX64K_00000" },
155 { 0x0258, "IA32_MTRR_FIX16K_80000" },
156 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
157 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
158 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
159 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
160 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
161 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
162 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
163 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
164 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
165 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
166 { 0x0400, "IA32_MC0_CTL" },
167 { 0x0401, "IA32_MC0_STATUS" },
168 { 0x0402, "IA32_MC0_ADDR" },
169 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
170 { 0x0404, "IA32_MC1_CTL" },
171 { 0x0405, "IA32_MC1_STATUS" },
172 { 0x0406, "IA32_MC1_ADDR" },
173 //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO
174 { 0x0408, "IA32_MC2_CTL" },
175 { 0x0409, "IA32_MC2_STATUS" },
176 { 0x040a, "IA32_MC2_ADDR" },
177 //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO
178 { 0x040c, "IA32_MC4_CTL" },
179 { 0x040d, "IA32_MC4_STATUS" },
180 { 0x040e, "IA32_MC4_ADDR" },
181 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
182 { 0x0410, "IA32_MC3_CTL" },
183 { 0x0411, "IA32_MC3_STATUS" },
184 { 0x0412, "IA32_MC3_ADDR" },
185 //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO
186 };
187
188 /* VIA C3 Nehemiah */
189 static const msr_entry_t model69x_global_msrs[] = {
190 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
191 { 0x002a, "EBL_CR_POWERON" },
192 { 0x00c1, "PERFCTR0" },
193 { 0x00c2, "PERFCTR1" },
194 { 0x011e, "BBL_CR_CTL3" },
195 { 0x0186, "EVNTSEL0" },
196 { 0x0187, "EVNTSEL1" },
197 { 0x0200, "IA32_MTRR_PHYSBASE0" },
198 { 0x0201, "IA32_MTRR_PHYSMASK0" },
199 { 0x0202, "IA32_MTRR_PHYSBASE1" },
200 { 0x0203, "IA32_MTRR_PHYSMASK1" },
201 { 0x0204, "IA32_MTRR_PHYSBASE2" },
202 { 0x0205, "IA32_MTRR_PHYSMASK2" },
203 { 0x0206, "IA32_MTRR_PHYSBASE3" },
204 { 0x0207, "IA32_MTRR_PHYSMASK3" },
205 { 0x0208, "IA32_MTRR_PHYSBASE4" },
206 { 0x0209, "IA32_MTRR_PHYSMASK4" },
207 { 0x020a, "IA32_MTRR_PHYSBASE5" },
208 { 0x020b, "IA32_MTRR_PHYSMASK5" },
209 { 0x020c, "IA32_MTRR_PHYSBASE6" },
210 { 0x020d, "IA32_MTRR_PHYSMASK6" },
211 { 0x020e, "IA32_MTRR_PHYSBASE7" },
212 { 0x020f, "IA32_MTRR_PHYSMASK7" },
213 { 0x0250, "IA32_MTRR_FIX64K_00000" },
214 { 0x0258, "IA32_MTRR_FIX16K_80000" },
215 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
216 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
217 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
218 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
219 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
220 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
221 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
222 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
223 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
224 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
225 { 0x1107, "FCR" },
226 { 0x1108, "FCR2" },
227 // WRITE ONLY { 0x1109, "FCR3" },
228 };
229
230 static const msr_entry_t model6bx_global_msrs[] = {
231 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
232 { 0x0017, "IA32_PLATFORM_ID" },
233 { 0x001b, "IA32_APIC_BASE" },
234 { 0x002a, "EBL_CR_POWERON" },
235 { 0x0033, "TEST_CTL" },
236 { 0x003f, "THERM_DIODE_OFFSET" },
237 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
238 { 0x008b, "IA32_BIOS_SIGN_ID" },
239 { 0x00c1, "PERFCTR0" },
240 { 0x00c2, "PERFCTR1" },
241 { 0x011e, "BBL_CR_CTL3" },
242 { 0x0179, "IA32_MCG_CAP" },
243 { 0x017a, "IA32_MCG_STATUS" },
244 { 0x0198, "IA32_PERF_STATUS" },
245 { 0x0199, "IA32_PERF_CONTROL" },
246 { 0x019a, "IA32_CLOCK_MODULATION" },
247 { 0x01a0, "IA32_MISC_ENABLES" },
248 { 0x01d9, "IA32_DEBUGCTL" },
249 { 0x0200, "IA32_MTRR_PHYSBASE0" },
250 { 0x0201, "IA32_MTRR_PHYSMASK0" },
251 { 0x0202, "IA32_MTRR_PHYSBASE1" },
252 { 0x0203, "IA32_MTRR_PHYSMASK1" },
253 { 0x0204, "IA32_MTRR_PHYSBASE2" },
254 { 0x0205, "IA32_MTRR_PHYSMASK2" },
255 { 0x0206, "IA32_MTRR_PHYSBASE3" },
256 { 0x0207, "IA32_MTRR_PHYSMASK3" },
257 { 0x0208, "IA32_MTRR_PHYSBASE4" },
258 { 0x0209, "IA32_MTRR_PHYSMASK4" },
259 { 0x020a, "IA32_MTRR_PHYSBASE5" },
260 { 0x020b, "IA32_MTRR_PHYSMASK5" },
261 { 0x020c, "IA32_MTRR_PHYSBASE6" },
262 { 0x020d, "IA32_MTRR_PHYSMASK6" },
263 { 0x020e, "IA32_MTRR_PHYSBASE7" },
264 { 0x020f, "IA32_MTRR_PHYSMASK7" },
265 { 0x0250, "IA32_MTRR_FIX64K_00000" },
266 { 0x0258, "IA32_MTRR_FIX16K_80000" },
267 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
268 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
269 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
270 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
271 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
272 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
273 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
274 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
275 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
276 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
277 { 0x0400, "IA32_MC0_CTL" },
278 { 0x0401, "IA32_MC0_STATUS" },
279 { 0x0402, "IA32_MC0_ADDR" },
280 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
281 { 0x040c, "IA32_MC4_CTL" },
282 { 0x040d, "IA32_MC4_STATUS" },
283 { 0x040e, "IA32_MC4_ADDR" },
284 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
285 };
286
287 static const msr_entry_t model6ex_global_msrs[] = {
288 { 0x0017, "IA32_PLATFORM_ID" },
289 { 0x002a, "EBL_CR_POWERON" },
290 { 0x00cd, "FSB_CLOCK_STS" },
291 { 0x00ce, "FSB_CLOCK_VCC" },
292 { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" },
293 { 0x00e3, "PMG_IO_BASE_ADDR" },
294 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
295 { 0x00ee, "EXT_CONFIG" },
296 { 0x011e, "BBL_CR_CTL3" },
297 { 0x0194, "CLOCK_FLEX_MAX" },
298 { 0x0198, "IA32_PERF_STATUS" },
299 { 0x01a0, "IA32_MISC_ENABLES" },
300 { 0x01aa, "PIC_SENS_CFG" },
301 { 0x0400, "IA32_MC0_CTL" },
302 { 0x0401, "IA32_MC0_STATUS" },
303 { 0x0402, "IA32_MC0_ADDR" },
304 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
305 { 0x040c, "IA32_MC4_CTL" },
306 { 0x040d, "IA32_MC4_STATUS" },
307 { 0x040e, "IA32_MC4_ADDR" },
308 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
309 };
310
311 static const msr_entry_t model6ex_per_core_msrs[] = {
312 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
313 { 0x001b, "IA32_APIC_BASE" },
314 { 0x003a, "IA32_FEATURE_CONTROL" },
315 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
316 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
317 { 0x008b, "IA32_BIOS_SIGN_ID" },
318 { 0x00e7, "IA32_MPERF" },
319 { 0x00e8, "IA32_APERF" },
320 { 0x00fe, "IA32_MTRRCAP" },
321 { 0x015f, "DTS_CAL_CTRL" },
322 { 0x0179, "IA32_MCG_CAP" },
323 { 0x017a, "IA32_MCG_STATUS" },
324 { 0x0199, "IA32_PERF_CONTROL" },
325 { 0x019a, "IA32_CLOCK_MODULATION" },
326 { 0x019b, "IA32_THERM_INTERRUPT" },
327 { 0x019c, "IA32_THERM_STATUS" },
328 { 0x019d, "GV_THERM" },
329 { 0x01d9, "IA32_DEBUGCTL" },
330 { 0x0200, "IA32_MTRR_PHYSBASE0" },
331 { 0x0201, "IA32_MTRR_PHYSMASK0" },
332 { 0x0202, "IA32_MTRR_PHYSBASE1" },
333 { 0x0203, "IA32_MTRR_PHYSMASK1" },
334 { 0x0204, "IA32_MTRR_PHYSBASE2" },
335 { 0x0205, "IA32_MTRR_PHYSMASK2" },
336 { 0x0206, "IA32_MTRR_PHYSBASE3" },
337 { 0x0207, "IA32_MTRR_PHYSMASK3" },
338 { 0x0208, "IA32_MTRR_PHYSBASE4" },
339 { 0x0209, "IA32_MTRR_PHYSMASK4" },
340 { 0x020a, "IA32_MTRR_PHYSBASE5" },
341 { 0x020b, "IA32_MTRR_PHYSMASK5" },
342 { 0x020c, "IA32_MTRR_PHYSBASE6" },
343 { 0x020d, "IA32_MTRR_PHYSMASK6" },
344 { 0x020e, "IA32_MTRR_PHYSBASE7" },
345 { 0x020f, "IA32_MTRR_PHYSMASK7" },
346 { 0x0250, "IA32_MTRR_FIX64K_00000" },
347 { 0x0258, "IA32_MTRR_FIX16K_80000" },
348 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
349 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
350 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
351 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
352 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
353 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
354 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
355 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
356 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
357 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
358 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
359 };
360
361 static const msr_entry_t model6fx_global_msrs[] = {
362 { 0x0017, "IA32_PLATFORM_ID" },
363 { 0x002a, "EBL_CR_POWERON" },
364 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
365 { 0x00a8, "EMTTM_CR_TABLE0" },
366 { 0x00a9, "EMTTM_CR_TABLE1" },
367 { 0x00aa, "EMTTM_CR_TABLE2" },
368 { 0x00ab, "EMTTM_CR_TABLE3" },
369 { 0x00ac, "EMTTM_CR_TABLE4" },
370 { 0x00ad, "EMTTM_CR_TABLE5" },
371 { 0x00cd, "FSB_CLOCK_STS" },
372 { 0x00e2, "PMG_CST_CONFIG_CONTROL" },
373 { 0x00e3, "PMG_IO_BASE_ADDR" },
374 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
375 { 0x00ee, "EXT_CONFIG" },
376 { 0x011e, "BBL_CR_CTL3" },
377 { 0x0194, "CLOCK_FLEX_MAX" },
378 { 0x0198, "IA32_PERF_STATUS" },
379 { 0x01a0, "IA32_MISC_ENABLES" },
380 { 0x01aa, "PIC_SENS_CFG" },
381 { 0x0400, "IA32_MC0_CTL" },
382 { 0x0401, "IA32_MC0_STATUS" },
383 { 0x0402, "IA32_MC0_ADDR" },
384 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
385 { 0x040c, "IA32_MC4_CTL" },
386 { 0x040d, "IA32_MC4_STATUS" },
387 { 0x040e, "IA32_MC4_ADDR" },
388 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
389 };
390
391 static const msr_entry_t model6fx_per_core_msrs[] = {
392 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
393 { 0x001b, "IA32_APIC_BASE" },
394 { 0x003a, "IA32_FEATURE_CONTROL" },
395 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
396 { 0x008b, "IA32_BIOS_SIGN_ID" },
397 { 0x00e1, "SMM_CST_MISC_INFO" },
398 { 0x00e7, "IA32_MPERF" },
399 { 0x00e8, "IA32_APERF" },
400 { 0x00fe, "IA32_MTRRCAP" },
401 { 0x0179, "IA32_MCG_CAP" },
402 { 0x017a, "IA32_MCG_STATUS" },
403 { 0x0199, "IA32_PERF_CONTROL" },
404 { 0x019a, "IA32_THERM_CTL" },
405 { 0x019b, "IA32_THERM_INTERRUPT" },
406 { 0x019c, "IA32_THERM_STATUS" },
407 { 0x019d, "MSR_THERM2_CTL" },
408 { 0x01d9, "IA32_DEBUGCTL" },
409 { 0x0200, "IA32_MTRR_PHYSBASE0" },
410 { 0x0201, "IA32_MTRR_PHYSMASK0" },
411 { 0x0202, "IA32_MTRR_PHYSBASE1" },
412 { 0x0203, "IA32_MTRR_PHYSMASK1" },
413 { 0x0204, "IA32_MTRR_PHYSBASE2" },
414 { 0x0205, "IA32_MTRR_PHYSMASK2" },
415 { 0x0206, "IA32_MTRR_PHYSBASE3" },
416 { 0x0207, "IA32_MTRR_PHYSMASK3" },
417 { 0x0208, "IA32_MTRR_PHYSBASE4" },
418 { 0x0209, "IA32_MTRR_PHYSMASK4" },
419 { 0x020a, "IA32_MTRR_PHYSBASE5" },
420 { 0x020b, "IA32_MTRR_PHYSMASK5" },
421 { 0x020c, "IA32_MTRR_PHYSBASE6" },
422 { 0x020d, "IA32_MTRR_PHYSMASK6" },
423 { 0x020e, "IA32_MTRR_PHYSBASE7" },
424 { 0x020f, "IA32_MTRR_PHYSMASK7" },
425 { 0x0250, "IA32_MTRR_FIX64K_00000" },
426 { 0x0258, "IA32_MTRR_FIX16K_80000" },
427 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
428 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
429 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
430 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
431 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
432 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
433 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
434 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
435 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
436 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
437 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
438 };
439
440 /* Pentium 4 and XEON */
441 /*
442 * All MSRs per
443 *
444 * Intel 64 and IA-32 Architectures Software Developer's Manual
445 * Volume 3B: System Programming Guide, Part 2
446 *
447 * Table B-5, B-7
448 */
449 static const msr_entry_t modelf2x_global_msrs[] = {
450 { 0x0000, "IA32_P5_MC_ADDR" },
451 { 0x0001, "IA32_P5_MC_TYPE" },
452 /* 0x6: Not available in model 2. */
453 { 0x0017, "IA32_PLATFORM_ID" },
454 { 0x002a, "MSR_EBC_HARD_POWERON" },
455 { 0x002b, "MSR_EBC_SOFT_POWERON" },
456 /* 0x2c: Not available in model 2. */
457 // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
458 { 0x019c, "IA32_THERM_STATUS" },
459 /* 0x19d: Not available in model 2. */
460 { 0x01a0, "IA32_MISC_ENABLE" },
461 /* 0x1a1: Not available in model 2. */
462 { 0x0200, "IA32_MTRR_PHYSBASE0" },
463 { 0x0201, "IA32_MTRR_PHYSMASK0" },
464 { 0x0202, "IA32_MTRR_PHYSBASE1" },
465 { 0x0203, "IA32_MTRR_PHYSMASK1" },
466 { 0x0204, "IA32_MTRR_PHYSBASE2" },
467 { 0x0205, "IA32_MTRR_PHYSMASK2" },
468 { 0x0206, "IA32_MTRR_PHYSBASE3" },
469 { 0x0207, "IA32_MTRR_PHYSMASK3" },
470 { 0x0208, "IA32_MTRR_PHYSBASE4" },
471 { 0x0209, "IA32_MTRR_PHYSMASK4" },
472 { 0x020a, "IA32_MTRR_PHYSBASE5" },
473 { 0x020b, "IA32_MTRR_PHYSMASK5" },
474 { 0x020c, "IA32_MTRR_PHYSBASE6" },
475 { 0x020d, "IA32_MTRR_PHYSMASK6" },
476 { 0x020e, "IA32_MTRR_PHYSBASE7" },
477 { 0x020f, "IA32_MTRR_PHYSMASK7" },
478 { 0x0250, "IA32_MTRR_FIX64K_00000" },
479 { 0x0258, "IA32_MTRR_FIX16K_80000" },
480 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
481 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
482 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
483 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
484 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
485 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
486 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
487 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
488 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
489 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
490 { 0x0300, "MSR_BPU_COUNTER0" },
491 { 0x0301, "MSR_BPU_COUNTER1" },
492 { 0x0302, "MSR_BPU_COUNTER2" },
493 { 0x0303, "MSR_BPU_COUNTER3" },
494 { 0x0304, "MSR_MS_COUNTER0" },
495 { 0x0305, "MSR_MS_COUNTER1" },
496 { 0x0306, "MSR_MS_COUNTER2" },
497 { 0x0307, "MSR_MS_COUNTER3" },
498 { 0x0308, "MSR_FLAME_COUNTER0" },
499 { 0x0309, "MSR_FLAME_COUNTER1" },
500 { 0x030a, "MSR_FLAME_COUNTER2" },
501 { 0x030b, "MSR_FLAME_COUNTER3" },
502 { 0x030c, "MSR_IQ_COUNTER0" },
503 { 0x030d, "MSR_IQ_COUNTER1" },
504 { 0x030e, "MSR_IQ_COUNTER2" },
505 { 0x030f, "MSR_IQ_COUNTER3" },
506 { 0x0310, "MSR_IQ_COUNTER4" },
507 { 0x0311, "MSR_IQ_COUNTER5" },
508 { 0x0360, "MSR_BPU_CCCR0" },
509 { 0x0361, "MSR_BPU_CCCR1" },
510 { 0x0362, "MSR_BPU_CCCR2" },
511 { 0x0363, "MSR_BPU_CCCR3" },
512 { 0x0364, "MSR_MS_CCCR0" },
513 { 0x0365, "MSR_MS_CCCR1" },
514 { 0x0366, "MSR_MS_CCCR2" },
515 { 0x0367, "MSR_MS_CCCR3" },
516 { 0x0368, "MSR_FLAME_CCCR0" },
517 { 0x0369, "MSR_FLAME_CCCR1" },
518 { 0x036a, "MSR_FLAME_CCCR2" },
519 { 0x036b, "MSR_FLAME_CCCR3" },
520 { 0x036c, "MSR_IQ_CCCR0" },
521 { 0x036d, "MSR_IQ_CCCR1" },
522 { 0x036e, "MSR_IQ_CCCR2" },
523 { 0x036f, "MSR_IQ_CCCR3" },
524 { 0x0370, "MSR_IQ_CCCR4" },
525 { 0x0371, "MSR_IQ_CCCR5" },
526 { 0x03a0, "MSR_BSU_ESCR0" },
527 { 0x03a1, "MSR_BSU_ESCR1" },
528 { 0x03a2, "MSR_FSB_ESCR0" },
529 { 0x03a3, "MSR_FSB_ESCR1" },
530 { 0x03a4, "MSR_FIRM_ESCR0" },
531 { 0x03a5, "MSR_FIRM_ESCR1" },
532 { 0x03a6, "MSR_FLAME_ESCR0" },
533 { 0x03a7, "MSR_FLAME_ESCR1" },
534 { 0x03a8, "MSR_DAC_ESCR0" },
535 { 0x03a9, "MSR_DAC_ESCR1" },
536 { 0x03aa, "MSR_MOB_ESCR0" },
537 { 0x03ab, "MSR_MOB_ESCR1" },
538 { 0x03ac, "MSR_PMH_ESCR0" },
539 { 0x03ad, "MSR_PMH_ESCR1" },
540 { 0x03ae, "MSR_SAAT_ESCR0" },
541 { 0x03af, "MSR_SAAT_ESCR1" },
542 { 0x03b0, "MSR_U2L_ESCR0" },
543 { 0x03b1, "MSR_U2L_ESCR1" },
544 { 0x03b2, "MSR_BPU_ESCR0" },
545 { 0x03b3, "MSR_BPU_ESCR1" },
546 { 0x03b4, "MSR_IS_ESCR0" },
547 { 0x03b5, "MSR_BPU_ESCR1" },
548 { 0x03b6, "MSR_ITLB_ESCR0" },
549 { 0x03b7, "MSR_ITLB_ESCR1" },
550 { 0x03b8, "MSR_CRU_ESCR0" },
551 { 0x03b9, "MSR_CRU_ESCR1" },
552 { 0x03ba, "MSR_IQ_ESCR0" },
553 { 0x03bb, "MSR_IQ_ESCR1" },
554 { 0x03bc, "MSR_RAT_ESCR0" },
555 { 0x03bd, "MSR_RAT_ESCR1" },
556 { 0x03be, "MSR_SSU_ESCR0" },
557 { 0x03c0, "MSR_MS_ESCR0" },
558 { 0x03c1, "MSR_MS_ESCR1" },
559 { 0x03c2, "MSR_TBPU_ESCR0" },
560 { 0x03c3, "MSR_TBPU_ESCR1" },
561 { 0x03c4, "MSR_TC_ESCR0" },
562 { 0x03c5, "MSR_TC_ESCR1" },
563 { 0x03c8, "MSR_IX_ESCR0" },
564 { 0x03c9, "MSR_IX_ESCR1" },
565 { 0x03ca, "MSR_ALF_ESCR0" },
566 { 0x03cb, "MSR_ALF_ESCR1" },
567 { 0x03cc, "MSR_CRU_ESCR2" },
568 { 0x03cd, "MSR_CRU_ESCR3" },
569 { 0x03e0, "MSR_CRU_ESCR4" },
570 { 0x03e1, "MSR_CRU_ESCR5" },
571 { 0x03f0, "MSR_TC_PRECISE_EVENT" },
572 { 0x03f1, "MSR_PEBS_ENABLE" },
573 { 0x03f2, "MSR_PEBS_MATRIX_VERT" },
574
575 /*
576 * All MCX_ADDR and MCX_MISC MSRs depend on a bit being
577 * set in MCX_STATUS.
578 */
579 { 0x400, "IA32_MC0_CTL" },
580 { 0x401, "IA32_MC0_STATUS" },
581 { 0x402, "IA32_MC0_ADDR" },
582 { 0x403, "IA32_MC0_MISC" },
583 { 0x404, "IA32_MC1_CTL" },
584 { 0x405, "IA32_MC1_STATUS" },
585 { 0x406, "IA32_MC1_ADDR" },
586 { 0x407, "IA32_MC1_MISC" },
587 { 0x408, "IA32_MC2_CTL" },
588 { 0x409, "IA32_MC2_STATUS" },
589 { 0x40a, "IA32_MC2_ADDR" },
590 { 0x40b, "IA32_MC2_MISC" },
591 { 0x40c, "IA32_MC3_CTL" },
592 { 0x40d, "IA32_MC3_STATUS" },
593 { 0x40e, "IA32_MC3_ADDR" },
594 { 0x40f, "IA32_MC3_MISC" },
595 { 0x410, "IA32_MC4_CTL" },
596 { 0x411, "IA32_MC4_STATUS" },
597 { 0x412, "IA32_MC4_ADDR" },
598 { 0x413, "IA32_MC4_MISC" },
599 };
600
601 static const msr_entry_t modelf2x_per_core_msrs[] = {
602 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
603 { 0x001b, "IA32_APIC_BASE" },
604 /* 0x3a: Not available in model 2. */
605 { 0x008b, "IA32_BIOS_SIGN_ID" },
606 /* 0x9b: Not available in model 2. */
607 { 0x00fe, "IA32_MTRRCAP" },
608 { 0x0174, "IA32_SYSENTER_CS" },
609 { 0x0175, "IA32_SYSENTER_ESP" },
610 { 0x0176, "IA32_SYSENTER_EIP" },
611 { 0x0179, "IA32_MCG_CAP" },
612 { 0x017a, "IA32_MCG_STATUS" },
613 { 0x017b, "IA32_MCG_CTL" },
614 { 0x0180, "MSR_MCG_RAX" },
615 { 0x0181, "MSR_MCG_RBX" },
616 { 0x0182, "MSR_MCG_RCX" },
617 { 0x0183, "MSR_MCG_RDX" },
618 { 0x0184, "MSR_MCG_RSI" },
619 { 0x0185, "MSR_MCG_RDI" },
620 { 0x0186, "MSR_MCG_RBP" },
621 { 0x0187, "MSR_MCG_RSP" },
622 { 0x0188, "MSR_MCG_RFLAGS" },
623 { 0x0189, "MSR_MCG_RIP" },
624 { 0x018a, "MSR_MCG_MISC" },
625 /* 0x18b-0x18f: Reserved */
626 { 0x0190, "MSR_MCG_R8" },
627 { 0x0191, "MSR_MCG_R9" },
628 { 0x0192, "MSR_MCG_R10" },
629 { 0x0193, "MSR_MCG_R11" },
630 { 0x0194, "MSR_MCG_R12" },
631 { 0x0195, "MSR_MCG_R13" },
632 { 0x0196, "MSR_MCG_R14" },
633 { 0x0197, "MSR_MCG_R15" },
634 /* 0x198: Not available in model 2. */
635 /* 0x199: Not available in model 2. */
636 { 0x019a, "IA32_CLOCK_MODULATION" },
637 { 0x019b, "IA32_THERM_INTERRUPT" },
638 { 0x01a0, "IA32_MISC_ENABLE" },
639 { 0x01d7, "MSR_LER_FROM_LIP" },
640 { 0x01d8, "MSR_LER_TO_LIP" },
641 { 0x01d9, "MSR_DEBUGCTLA" },
642 { 0x01da, "MSR_LASTBRANCH_TOS" },
643 { 0x01db, "MSR_LASTBRANCH_0" },
644 { 0x01dd, "MSR_LASTBRANCH_2" },
645 { 0x01de, "MSR_LASTBRANCH_3" },
646 { 0x0277, "IA32_PAT" },
647 /* 0x480-0x48b : Not available in model 2. */
648 { 0x0600, "IA32_DS_AREA" },
649 /* 0x0680 - 0x06cf Branch Records Skipped */
650 };
651
652 static const msr_entry_t modelf4x_global_msrs[] = {
653 { 0x0000, "IA32_P5_MC_ADDR" },
654 { 0x0001, "IA32_P5_MC_TYPE" },
655 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
656 { 0x0017, "IA32_PLATFORM_ID" },
657 { 0x002a, "MSR_EBC_HARD_POWERON" },
658 { 0x002b, "MSR_EBC_SOFT_POWERON" },
659 { 0x002c, "MSR_EBC_FREQUENCY_ID" },
660 // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
661 { 0x019c, "IA32_THERM_STATUS" },
662 { 0x019d, "MSR_THERM2_CTL" },
663 { 0x01a0, "IA32_MISC_ENABLE" },
664 { 0x01a1, "MSR_PLATFORM_BRV" },
665 { 0x0200, "IA32_MTRR_PHYSBASE0" },
666 { 0x0201, "IA32_MTRR_PHYSMASK0" },
667 { 0x0202, "IA32_MTRR_PHYSBASE1" },
668 { 0x0203, "IA32_MTRR_PHYSMASK1" },
669 { 0x0204, "IA32_MTRR_PHYSBASE2" },
670 { 0x0205, "IA32_MTRR_PHYSMASK2" },
671 { 0x0206, "IA32_MTRR_PHYSBASE3" },
672 { 0x0207, "IA32_MTRR_PHYSMASK3" },
673 { 0x0208, "IA32_MTRR_PHYSBASE4" },
674 { 0x0209, "IA32_MTRR_PHYSMASK4" },
675 { 0x020a, "IA32_MTRR_PHYSBASE5" },
676 { 0x020b, "IA32_MTRR_PHYSMASK5" },
677 { 0x020c, "IA32_MTRR_PHYSBASE6" },
678 { 0x020d, "IA32_MTRR_PHYSMASK6" },
679 { 0x020e, "IA32_MTRR_PHYSBASE7" },
680 { 0x020f, "IA32_MTRR_PHYSMASK7" },
681 { 0x0250, "IA32_MTRR_FIX64K_00000" },
682 { 0x0258, "IA32_MTRR_FIX16K_80000" },
683 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
684 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
685 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
686 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
687 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
688 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
689 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
690 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
691 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
692 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
693 { 0x0300, "MSR_BPU_COUNTER0" },
694 { 0x0301, "MSR_BPU_COUNTER1" },
695 { 0x0302, "MSR_BPU_COUNTER2" },
696 { 0x0303, "MSR_BPU_COUNTER3" },
697 /* Skipped through 0x3ff for now*/
698
699 /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
700 * set in MCX_STATUS */
701 { 0x400, "IA32_MC0_CTL" },
702 { 0x401, "IA32_MC0_STATUS" },
703 { 0x402, "IA32_MC0_ADDR" },
704 { 0x403, "IA32_MC0_MISC" },
705 { 0x404, "IA32_MC1_CTL" },
706 { 0x405, "IA32_MC1_STATUS" },
707 { 0x406, "IA32_MC1_ADDR" },
708 { 0x407, "IA32_MC1_MISC" },
709 { 0x408, "IA32_MC2_CTL" },
710 { 0x409, "IA32_MC2_STATUS" },
711 { 0x40a, "IA32_MC2_ADDR" },
712 { 0x40b, "IA32_MC2_MISC" },
713 { 0x40c, "IA32_MC3_CTL" },
714 { 0x40d, "IA32_MC3_STATUS" },
715 { 0x40e, "IA32_MC3_ADDR" },
716 { 0x40f, "IA32_MC3_MISC" },
717 { 0x410, "IA32_MC4_CTL" },
718 { 0x411, "IA32_MC4_STATUS" },
719 { 0x412, "IA32_MC4_ADDR" },
720 { 0x413, "IA32_MC4_MISC" },
721 };
722
723 static const msr_entry_t modelf4x_per_core_msrs[] = {
724 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
725 { 0x001b, "IA32_APIC_BASE" },
726 { 0x003a, "IA32_FEATURE_CONTROL" },
727 { 0x008b, "IA32_BIOS_SIGN_ID" },
728 { 0x009b, "IA32_SMM_MONITOR_CTL" },
729 { 0x00fe, "IA32_MTRRCAP" },
730 { 0x0174, "IA32_SYSENTER_CS" },
731 { 0x0175, "IA32_SYSENTER_ESP" },
732 { 0x0176, "IA32_SYSENTER_EIP" },
733 { 0x0179, "IA32_MCG_CAP" },
734 { 0x017a, "IA32_MCG_STATUS" },
735 { 0x0180, "MSR_MCG_RAX" },
736 { 0x0181, "MSR_MCG_RBX" },
737 { 0x0182, "MSR_MCG_RCX" },
738 { 0x0183, "MSR_MCG_RDX" },
739 { 0x0184, "MSR_MCG_RSI" },
740 { 0x0185, "MSR_MCG_RDI" },
741 { 0x0186, "MSR_MCG_RBP" },
742 { 0x0187, "MSR_MCG_RSP" },
743 { 0x0188, "MSR_MCG_RFLAGS" },
744 { 0x0189, "MSR_MCG_RIP" },
745 { 0x018a, "MSR_MCG_MISC" },
746 // 0x18b-f Reserved
747 { 0x0190, "MSR_MCG_R8" },
748 { 0x0191, "MSR_MCG_R9" },
749 { 0x0192, "MSR_MCG_R10" },
750 { 0x0193, "MSR_MCG_R11" },
751 { 0x0194, "MSR_MCG_R12" },
752 { 0x0195, "MSR_MCG_R13" },
753 { 0x0196, "MSR_MCG_R14" },
754 { 0x0197, "MSR_MCG_R15" },
755 { 0x0198, "IA32_PERF_STATUS" },
756 { 0x0199, "IA32_PERF_CTL" },
757 { 0x019a, "IA32_CLOCK_MODULATION" },
758 { 0x019b, "IA32_THERM_INTERRUPT" },
759 { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
760 { 0x01d7, "MSR_LER_FROM_LIP" },
761 { 0x01d8, "MSR_LER_TO_LIP" },
762 { 0x01d9, "MSR_DEBUGCTLA" },
763 { 0x01da, "MSR_LASTBRANCH_TOS" },
764 { 0x0277, "IA32_PAT" },
765 /** Virtualization
766 { 0x480, "IA32_VMX_BASIC" },
767 through
768 { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
769 Not implemented in my CPU
770 */
771 { 0x0600, "IA32_DS_AREA" },
772 /* 0x0680 - 0x06cf Branch Records Skipped */
773
774 };
775
776 /* Atom N455
777 *
778 * This should apply to the following processors:
779 * 06_1CH
780 * 06_26H
781 * 06_27H
782 * 06_35
783 * 06_36
784 */
785 /*
786 * All MSRs per
787 *
788 * Intel 64 and IA-32 Architectures Software Developer's Manual
789 * Volume 3C: System Programming Guide, Part 3
790 * Order Number 326019
791 * January 2013
792 *
793 * Table 35-4, 35-5
794 *
795 * For now it has only been tested with 06_1CH.
796 */
797 static const msr_entry_t model6_atom_global_msrs[] = {
798 { 0x0000, "IA32_P5_MC_ADDR" },
799 { 0x0001, "IA32_P5_MC_TYPE" },
800 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
801 { 0x0017, "IA32_PLATFORM_ID" },
802 { 0x002a, "MSR_EBC_HARD_POWERON" },
803 { 0x00cd, "MSR_FSB_FREQ" },
804 { 0x00fe, "IA32_MTRRCAP" },
805 { 0x011e, "MSR_BBL_CR_CTL3" },
806 { 0x0198, "IA32_PERF_STATUS" },
807 { 0x019d, "MSR_THERM2_CTL" },
808 { 0x0200, "IA32_MTRR_PHYSBASE0" },
809 { 0x0201, "IA32_MTRR_PHYSMASK0" },
810 { 0x0202, "IA32_MTRR_PHYSBASE1" },
811 { 0x0203, "IA32_MTRR_PHYSMASK1" },
812 { 0x0204, "IA32_MTRR_PHYSBASE2" },
813 { 0x0205, "IA32_MTRR_PHYSMASK2" },
814 { 0x0206, "IA32_MTRR_PHYSBASE3" },
815 { 0x0207, "IA32_MTRR_PHYSMASK3" },
816 { 0x0208, "IA32_MTRR_PHYSBASE4" },
817 { 0x0209, "IA32_MTRR_PHYSMASK4" },
818 { 0x020a, "IA32_MTRR_PHYSBASE5" },
819 { 0x020b, "IA32_MTRR_PHYSMASK5" },
820 { 0x020c, "IA32_MTRR_PHYSBASE6" },
821 { 0x020d, "IA32_MTRR_PHYSMASK6" },
822 { 0x020e, "IA32_MTRR_PHYSBASE7" },
823 { 0x020f, "IA32_MTRR_PHYSMASK7" },
824 { 0x0250, "IA32_MTRR_FIX64K_00000" },
825 { 0x0258, "IA32_MTRR_FIX16K_80000" },
826 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
827 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
828 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
829 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
830 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
831 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
832 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
833 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
834 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
835 { 0x0345, "IA32_PERF_CAPABILITIES" },
836 { 0x400, "IA32_MC0_CTL" },
837 { 0x401, "IA32_MC0_STATUS" },
838 { 0x402, "IA32_MC0_ADDR" },
839 { 0x404, "IA32_MC1_CTL" },
840 { 0x405, "IA32_MC1_STATUS" },
841 { 0x408, "IA32_MC2_CTL" },
842 { 0x409, "IA32_MC2_STATUS" },
843 { 0x40a, "IA32_MC2_ADDR" },
844 { 0x40c, "IA32_MC3_CTL" },
845 { 0x40d, "IA32_MC3_STATUS" },
846 { 0x40e, "IA32_MC3_ADDR" },
847 { 0x410, "IA32_MC4_CTL" },
848 { 0x411, "IA32_MC4_STATUS" },
849 { 0x412, "IA32_MC4_ADDR" },
850 /*
851 * Only 06_27C has the following MSRs
852 */
853 /*
854 { 0x03f8, "MSR_PKG_C2_RESIDENCY" },
855 { 0x03f9, "MSR_PKG_C4_RESIDENCY" },
856 { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
857 */
858 };
859
860 static const msr_entry_t model6_atom_per_core_msrs[] = {
861 { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
862 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
863 { 0x001b, "IA32_APIC_BASE" },
864 { 0x003a, "IA32_FEATURE_CONTROL" },
865 { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
866 { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
867 { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
868 { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
869 { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
870 { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
871 { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
872 { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
873 { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
874 { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
875 { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
876 { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
877 { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
878 { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
879 { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
880 { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
881 /* Write register */
882 /*
883 { 0x0079, "IA32_BIOS_UPDT_TRIG" },
884 */
885 { 0x008b, "IA32_BIOS_SIGN_ID" },
886 { 0x00c1, "IA32_PMC0" },
887 { 0x00c2, "IA32_PMC1" },
888 { 0x00e7, "IA32_MPERF" },
889 { 0x00e8, "IA32_APERF" },
890 { 0x0174, "IA32_SYSENTER_CS" },
891 { 0x0175, "IA32_SYSENTER_ESP" },
892 { 0x0176, "IA32_SYSENTER_EIP" },
893 { 0x017a, "IA32_MCG_STATUS" },
894 { 0x0186, "IA32_PERF_EVNTSEL0" },
895 { 0x0187, "IA32_PERF_EVNTSEL1" },
896 { 0x0199, "IA32_PERF_CONTROL" },
897 { 0x019a, "IA32_CLOCK_MODULATION" },
898 { 0x019b, "IA32_THERM_INTERRUPT" },
899 { 0x019c, "IA32_THERM_STATUS" },
900 { 0x01a0, "IA32_MISC_ENABLES" },
901 { 0x01c9, "MSR_LASTBRANCH_TOS" },
902 { 0x01d9, "IA32_DEBUGCTL" },
903 { 0x01dd, "MSR_LER_FROM_LIP" },
904 { 0x01de, "MSR_LER_TO_LIP" },
905 { 0x0277, "IA32_PAT" },
906 { 0x0309, "IA32_FIXED_CTR0" },
907 { 0x030a, "IA32_FIXED_CTR1" },
908 { 0x030b, "IA32_FIXED_CTR2" },
909 { 0x038d, "IA32_FIXED_CTR_CTRL" },
910 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
911 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
912 { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
913 { 0x03f1, "MSR_PEBS_ENABLE" },
914 { 0x0480, "IA32_VMX_BASIC" },
915 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
916 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
917 { 0x0483, "IA32_VMX_EXIT_CTLS" },
918 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
919 { 0x0485, "IA32_VMX_MISC" },
920 { 0x0486, "IA32_VMX_CR0_FIXED0" },
921 { 0x0487, "IA32_VMX_CR0_FIXED1" },
922 { 0x0488, "IA32_VMX_CR4_FIXED0" },
923 { 0x0489, "IA32_VMX_CR4_FIXED1" },
924 { 0x048a, "IA32_VMX_VMCS_ENUM" },
925 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
926 { 0x0600, "IA32_DS_AREA" },
927 };
928
929 typedef struct {
930 unsigned int model;
931 const msr_entry_t *global_msrs;
932 unsigned int num_global_msrs;
933 const msr_entry_t *per_core_msrs;
934 unsigned int num_per_core_msrs;
935 } cpu_t;
936
937 cpu_t cpulist[] = {
938 { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 },
939 { 0x00690, model69x_global_msrs, ARRAY_SIZE(model69x_global_msrs), NULL, 0 },
940 { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
941 { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
942 { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
943 { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
944 { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
945 { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
946 };
947
948 cpu_t *cpu = NULL;
949
950 /* Get CPU family and model, not the stepping
951 * (TODO: extended family/model)
952 */
953 id = cpuid(1) & 0xfffff0;
954 for (i = 0; i < ARRAY_SIZE(cpulist); i++) {
955 if(cpulist[i].model == id) {
956 cpu = &cpulist[i];
957 break;
958 }
959 }
960
961 if (!cpu) {
962 printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id);
963 return -1;
964 }
965
966 #ifndef __DARWIN__
967 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
968 if (fd_msr < 0) {
969 perror("Error while opening /dev/cpu/0/msr");
970 printf("Did you run 'modprobe msr'?\n");
971 return -1;
972 }
973 #endif
974
975 printf("\n===================== SHARED MSRs (All Cores) =====================\n");
976
977 for (i = 0; i < cpu->num_global_msrs; i++) {
978 msr = rdmsr(cpu->global_msrs[i].number);
979 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
980 cpu->global_msrs[i].number, msr.hi, msr.lo,
981 cpu->global_msrs[i].name);
982 }
983
984 close(fd_msr);
985
986 for (core = 0; core < 8; core++) {
987 #ifndef __DARWIN__
988 char msrfilename[64];
989 memset(msrfilename, 0, 64);
990 sprintf(msrfilename, "/dev/cpu/%u/msr", core);
991
992 fd_msr = open(msrfilename, O_RDWR);
993
994 /* If the file is not there, we're probably through. No error,
995 * since we successfully opened /dev/cpu/0/msr before.
996 */
997 if (fd_msr < 0)
998 break;
999 #endif
1000 if (cpu->num_per_core_msrs)
1001 printf("\n====================== UNIQUE MSRs (core %u) ======================\n", core);
1002
1003 for (i = 0; i < cpu->num_per_core_msrs; i++) {
1004 msr = rdmsr(cpu->per_core_msrs[i].number);
1005 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
1006 cpu->per_core_msrs[i].number, msr.hi, msr.lo,
1007 cpu->per_core_msrs[i].name);
1008 }
1009 #ifndef __DARWIN__
1010 close(fd_msr);
1011 #endif
1012 }
1013
1014 #ifndef __DARWIN__
1015 if (msr_readerror)
1016 printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
1017 #endif
1018 return 0;
1019 }
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