src/arch/x86/mpspec.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/path.h>
   5 #include <device/pci_ids.h>
   6 #include <arch/ioapic.h>
   7 #include <arch/smp/mpspec.h>
   8 #include <string.h>
   9 #include <arch/cpu.h>
  10 #include <cpu/cpu.h>
  11 #include <cpu/x86/lapic.h>
  12 #include <drivers/generic/ioapic/chip.h>
  13
  14 /* Initialize the specified "mc" struct with initial values. */
  15 void mptable_init(struct mp_config_table *mc)
  16 {
  17         int i;
  18         u32 lapic_addr = cpu_get_lapic_addr();
  19
  20         memset(mc, 0, sizeof(*mc));
  21
  22         memcpy(mc->mpc_signature, MPC_SIGNATURE, 4);
  23
  24         mc->mpc_length = sizeof(*mc);   /* Initially just the header size. */
  25         mc->mpc_spec = 0x04;            /* MultiProcessor specification 1.4 */
  26         mc->mpc_checksum = 0;           /* Not yet computed. */
  27         mc->mpc_oemptr = 0;
  28         mc->mpc_oemsize = 0;
  29         mc->mpc_entry_count = 0;        /* No entries yet... */
  30         mc->mpc_lapic = lapic_addr;
  31         mc->mpe_length = 0;
  32         mc->mpe_checksum = 0;
  33         mc->reserved = 0;
  34
  35         strncpy(mc->mpc_oem, CONFIG_MAINBOARD_VENDOR, 8);
  36         strncpy(mc->mpc_productid, CONFIG_MAINBOARD_PART_NUMBER, 12);
  37
  38         /*
  39          * The oem/productid fields are exactly 8/12 bytes long. If the resp.
  40          * entry is shorter, the remaining bytes are filled with spaces.
  41          */
  42         for (i = MIN(strlen(CONFIG_MAINBOARD_VENDOR), 8); i < 8; i++)
  43                 mc->mpc_oem[i] = ' ';
  44         for (i = MIN(strlen(CONFIG_MAINBOARD_PART_NUMBER), 12); i < 12; i++)
  45                 mc->mpc_productid[i] = ' ';
  46 }
  47
  48 static unsigned char smp_compute_checksum(void *v, int len)
  49 {
  50         unsigned char *bytes;
  51         unsigned char checksum;
  52         int i;
  53         bytes = v;
  54         checksum = 0;
  55         for (i = 0; i < len; i++)
  56                 checksum -= bytes[i];
  57         return checksum;
  58 }
  59
  60 static void *smp_write_floating_table_physaddr(uintptr_t addr,
  61         uintptr_t mpf_physptr, unsigned int virtualwire)
  62 {
  63         struct intel_mp_floating *mf;
  64         void *v;
  65
  66         v = (void *)addr;
  67         mf = v;
  68         mf->mpf_signature[0] = '_';
  69         mf->mpf_signature[1] = 'M';
  70         mf->mpf_signature[2] = 'P';
  71         mf->mpf_signature[3] = '_';
  72         mf->mpf_physptr = mpf_physptr;
  73         mf->mpf_length = 1;
  74         mf->mpf_specification = 4;
  75         mf->mpf_checksum = 0;
  76         mf->mpf_feature1 = 0;
  77         mf->mpf_feature2 = virtualwire?MP_FEATURE_PIC:MP_FEATURE_VIRTUALWIRE;
  78         mf->mpf_feature3 = 0;
  79         mf->mpf_feature4 = 0;
  80         mf->mpf_feature5 = 0;
  81         mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
  82         return v;
  83 }
  84
  85 void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire)
  86 {
  87         /* 16 byte align the table address */
  88         addr = (addr + 0xf) & (~0xf);
  89         return smp_write_floating_table_physaddr(addr, addr
  90                 + SMP_FLOATING_TABLE_LEN, virtualwire);
  91 }
  92
  93 void *smp_next_mpc_entry(struct mp_config_table *mc)
  94 {
  95         void *v;
  96         v = (void *)(((char *)mc) + mc->mpc_length);
  97
  98         return v;
  99 }
 100 static void smp_add_mpc_entry(struct mp_config_table *mc, u16 length)
 101 {
 102         mc->mpc_length += length;
 103         mc->mpc_entry_count++;
 104 }
 105
 106 void *smp_next_mpe_entry(struct mp_config_table *mc)
 107 {
 108         void *v;
 109         v = (void *)(((char *)mc) + mc->mpc_length + mc->mpe_length);
 110
 111         return v;
 112 }
 113 static void smp_add_mpe_entry(struct mp_config_table *mc, mpe_t mpe)
 114 {
 115         mc->mpe_length += mpe->mpe_length;
 116 }
 117
 118 /*
 119  * Type 0: Processor Entries:
 120  * Entry Type, LAPIC ID, LAPIC Version, CPU Flags EN/BP,
 121  * CPU Signature (Stepping, Model, Family), Feature Flags
 122  */
 123 void smp_write_processor(struct mp_config_table *mc,
 124         u8 apicid, u8 apicver, u8 cpuflag,
 125         u32 cpufeature, u32 featureflag)
 126 {
 127         struct mpc_config_processor *mpc;
 128         mpc = smp_next_mpc_entry(mc);
 129         memset(mpc, '\0', sizeof(*mpc));
 130         mpc->mpc_type = MP_PROCESSOR;
 131         mpc->mpc_apicid = apicid;
 132         mpc->mpc_apicver = apicver;
 133         mpc->mpc_cpuflag = cpuflag;
 134         mpc->mpc_cpufeature = cpufeature;
 135         mpc->mpc_featureflag = featureflag;
 136         smp_add_mpc_entry(mc, sizeof(*mpc));
 137 }
 138
 139 /*
 140  * If we assume a symmetric processor configuration we can
 141  * get all of the information we need to write the processor
 142  * entry from the bootstrap processor.
 143  * Plus I don't think linux really even cares.
 144  * Having the proper apicid's in the table so the non-bootstrap
 145  *  processors can be woken up should be enough.
 146  */
 147 void smp_write_processors(struct mp_config_table *mc)
 148 {
 149         int boot_apic_id;
 150         int order_id;
 151         unsigned int apic_version;
 152         unsigned int cpu_features;
 153         unsigned int cpu_feature_flags;
 154         struct device *cpu;
 155
 156         boot_apic_id = lapicid();
 157         apic_version = lapic_read(LAPIC_LVR) & 0xff;
 158         cpu_features = cpu_get_cpuid();
 159         cpu_feature_flags = cpu_get_feature_flags_edx();
 160         /* order the output of the cpus to fix a bug in kernel 2.6.11 */
 161         for (order_id = 0; order_id < 256; order_id++) {
 162                 for (cpu = all_devices; cpu; cpu = cpu->next) {
 163                         unsigned long cpu_flag;
 164                         if ((cpu->path.type != DEVICE_PATH_APIC) ||
 165                                 (cpu->bus->dev->path.type !=
 166                                         DEVICE_PATH_CPU_CLUSTER))
 167                                 continue;
 168
 169                         if (!cpu->enabled)
 170                                 continue;
 171
 172                         cpu_flag = MPC_CPU_ENABLED;
 173
 174                         if (boot_apic_id == cpu->path.apic.apic_id)
 175                                 cpu_flag = MPC_CPU_ENABLED
 176                                         | MPC_CPU_BOOTPROCESSOR;
 177
 178                         if (cpu->path.apic.apic_id == order_id) {
 179                                 smp_write_processor(mc,
 180                                         cpu->path.apic.apic_id, apic_version,
 181                                         cpu_flag, cpu_features,
 182                                         cpu_feature_flags
 183                                 );
 184                                 break;
 185                         }
 186                 }
 187         }
 188 }
 189
 190 /*
 191  * Type 1: Bus Entries:
 192  * Entry Type, Bus ID, Bus Type
 193  */
 194 static void smp_write_bus(struct mp_config_table *mc,
 195         u8 id, const char *bustype)
 196 {
 197         struct mpc_config_bus *mpc;
 198         mpc = smp_next_mpc_entry(mc);
 199         memset(mpc, '\0', sizeof(*mpc));
 200         mpc->mpc_type = MP_BUS;
 201         mpc->mpc_busid = id;
 202         memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
 203         smp_add_mpc_entry(mc, sizeof(*mpc));
 204 }
 205
 206 /*
 207  * Type 2: I/O APIC Entries:
 208  * Entry Type, APIC ID, Version,
 209  * APIC Flags:EN, Address
 210  */
 211 void smp_write_ioapic(struct mp_config_table *mc,
 212         u8 id, u8 ver, void *apicaddr)
 213 {
 214         struct mpc_config_ioapic *mpc;
 215         mpc = smp_next_mpc_entry(mc);
 216         memset(mpc, '\0', sizeof(*mpc));
 217         mpc->mpc_type = MP_IOAPIC;
 218         mpc->mpc_apicid = id;
 219         mpc->mpc_apicver = ver;
 220         mpc->mpc_flags = MPC_APIC_USABLE;
 221         mpc->mpc_apicaddr = apicaddr;
 222         smp_add_mpc_entry(mc, sizeof(*mpc));
 223 }
 224
 225 u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, void *apicaddr)
 226 {
 227         u8 id = get_ioapic_id(apicaddr);
 228         u8 ver = get_ioapic_version(apicaddr);
 229         smp_write_ioapic(mc, id, ver, apicaddr);
 230         return id;
 231 }
 232
 233 /*
 234  * Type 3: I/O Interrupt Table Entries:
 235  * Entry Type, Int Type, Int Polarity, Int Level,
 236  * Source Bus ID, Source Bus IRQ, Dest APIC ID, Dest PIN#
 237  */
 238 void smp_write_intsrc(struct mp_config_table *mc,
 239         u8 irqtype, u16 irqflag,
 240         u8 srcbus, u8 srcbusirq,
 241         u8 dstapic, u8 dstirq)
 242 {
 243         struct mpc_config_intsrc *mpc;
 244         mpc = smp_next_mpc_entry(mc);
 245         memset(mpc, '\0', sizeof(*mpc));
 246         mpc->mpc_type = MP_INTSRC;
 247         mpc->mpc_irqtype = irqtype;
 248         mpc->mpc_irqflag = irqflag;
 249         mpc->mpc_srcbus = srcbus;
 250         mpc->mpc_srcbusirq = srcbusirq;
 251         mpc->mpc_dstapic = dstapic;
 252         mpc->mpc_dstirq = dstirq;
 253         smp_add_mpc_entry(mc, sizeof(*mpc));
 254 }
 255
 256 /*
 257  * Type 3: I/O Interrupt Table Entries for PCI Devices:
 258  * This has the same fields as 'Type 3: I/O Interrupt Table Entries'
 259  * but the Source Bus IRQ field has a slightly different
 260  * definition:
 261  * Bits 1-0: PIRQ pin: INT_A# = 0, INT_B# = 1, INT_C# = 2, INT_D# = 3
 262  * Bits 2-6: Originating PCI Device Number (Not its parent bridge device number)
 263  * Bit 7: Reserved
 264  */
 265 void smp_write_pci_intsrc(struct mp_config_table *mc,
 266         u8 irqtype, u8 srcbus, u8 dev, u8 pirq,
 267         u8 dstapic, u8 dstirq)
 268 {
 269         u8 srcbusirq = (dev << 2) | pirq;
 270         printk(BIOS_SPEW,
 271                 "\tPCI srcbusirq = 0x%x from dev = 0x%x and pirq = %x\n",
 272                 srcbusirq, dev, pirq);
 273         smp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL
 274                 | MP_IRQ_POLARITY_LOW, srcbus, srcbusirq, dstapic, dstirq);
 275 }
 276
 277 void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
 278         u8 irqtype, u16 irqflag, struct device *dev,
 279         unsigned char dstapic, unsigned char *dstirq)
 280 {
 281         struct device *child;
 282
 283         int i;
 284         int srcbus;
 285         int slot;
 286
 287         struct bus *link;
 288         unsigned char dstirq_x[4];
 289
 290         for (link = dev->link_list; link; link = link->next) {
 291
 292                 child = link->children;
 293                 srcbus = link->secondary;
 294
 295                 while (child) {
 296                         if (child->path.type != DEVICE_PATH_PCI)
 297                                 goto next;
 298
 299                         slot = (child->path.pci.devfn >> 3);
 300                         /* round pins */
 301                         for (i = 0; i < 4; i++)
 302                                 dstirq_x[i] = dstirq[(i + slot) % 4];
 303
 304                         if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) {
 305                                 /* pci device */
 306                                 printk(BIOS_DEBUG, "route irq: %s\n",
 307                                         dev_path(child));
 308                                 for (i = 0; i < 4; i++)
 309                                         smp_write_intsrc(mc, irqtype, irqflag,
 310                                                 srcbus, (slot<<2)|i, dstapic,
 311                                                 dstirq_x[i]);
 312                                 goto next;
 313                         }
 314
 315                         switch (child->class>>8) {
 316                         case PCI_CLASS_BRIDGE_PCI:
 317                         case PCI_CLASS_BRIDGE_PCMCIA:
 318                         case PCI_CLASS_BRIDGE_CARDBUS:
 319                                 printk(BIOS_DEBUG, "route irq bridge: %s\n",
 320                                         dev_path(child));
 321                                 smp_write_intsrc_pci_bridge(mc, irqtype,
 322                                         irqflag, child, dstapic, dstirq_x);
 323                         }
 324
 325 next:
 326                         child = child->sibling;
 327                 }
 328
 329         }
 330 }
 331
 332 /*
 333  * Type 4: Local Interrupt Assignment Entries:
 334  * Entry Type, Int Type, Int Polarity, Int Level,
 335  * Source Bus ID, Source Bus IRQ, Dest LAPIC ID,
 336  * Dest LAPIC LINTIN#
 337  */
 338 void smp_write_lintsrc(struct mp_config_table *mc,
 339         u8 irqtype, u16 irqflag,
 340         u8 srcbusid, u8 srcbusirq,
 341         u8 destapic, u8 destapiclint)
 342 {
 343         struct mpc_config_lintsrc *mpc;
 344         mpc = smp_next_mpc_entry(mc);
 345         memset(mpc, '\0', sizeof(*mpc));
 346         mpc->mpc_type = MP_LINTSRC;
 347         mpc->mpc_irqtype = irqtype;
 348         mpc->mpc_irqflag = irqflag;
 349         mpc->mpc_srcbusid = srcbusid;
 350         mpc->mpc_srcbusirq = srcbusirq;
 351         mpc->mpc_destapic = destapic;
 352         mpc->mpc_destapiclint = destapiclint;
 353         smp_add_mpc_entry(mc, sizeof(*mpc));
 354 }
 355
 356 /*
 357  * Type 128: System Address Space Mapping Entries
 358  * Entry Type, Entry Length, Bus ID, Address Type,
 359  * Address Base Lo/Hi, Address Length Lo/Hi
 360  */
 361 void smp_write_address_space(struct mp_config_table *mc,
 362         u8 busid, u8 address_type,
 363         u32 address_base_low, u32 address_base_high,
 364         u32 address_length_low, u32 address_length_high)
 365 {
 366         struct mp_exten_system_address_space *mpe;
 367         mpe = smp_next_mpe_entry(mc);
 368         memset(mpe, '\0', sizeof(*mpe));
 369         mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE;
 370         mpe->mpe_length = sizeof(*mpe);
 371         mpe->mpe_busid = busid;
 372         mpe->mpe_address_type = address_type;
 373         mpe->mpe_address_base_low  = address_base_low;
 374         mpe->mpe_address_base_high = address_base_high;
 375         mpe->mpe_address_length_low  = address_length_low;
 376         mpe->mpe_address_length_high = address_length_high;
 377         smp_add_mpe_entry(mc, (mpe_t)mpe);
 378 }
 379
 380 /*
 381  * Type 129: Bus Hierarchy Descriptor Entry
 382  * Entry Type, Entry Length, Bus ID, Bus Info,
 383  * Parent Bus ID
 384  */
 385 void smp_write_bus_hierarchy(struct mp_config_table *mc,
 386         u8 busid, u8 bus_info, u8 parent_busid)
 387 {
 388         struct mp_exten_bus_hierarchy *mpe;
 389         mpe = smp_next_mpe_entry(mc);
 390         memset(mpe, '\0', sizeof(*mpe));
 391         mpe->mpe_type = MPE_BUS_HIERARCHY;
 392         mpe->mpe_length = sizeof(*mpe);
 393         mpe->mpe_busid = busid;
 394         mpe->mpe_bus_info = bus_info;
 395         mpe->mpe_parent_busid = parent_busid;
 396         smp_add_mpe_entry(mc, (mpe_t)mpe);
 397 }
 398
 399 /*
 400  * Type 130: Compatibility Bus Address Space Modifier Entry
 401  * Entry Type, Entry Length, Bus ID, Address Modifier
 402  * Predefined Range List
 403  */
 404 void smp_write_compatibility_address_space(struct mp_config_table *mc,
 405         u8 busid, u8 address_modifier,
 406         u32 range_list)
 407 {
 408         struct mp_exten_compatibility_address_space *mpe;
 409         mpe = smp_next_mpe_entry(mc);
 410         memset(mpe, '\0', sizeof(*mpe));
 411         mpe->mpe_type = MPE_COMPATIBILITY_ADDRESS_SPACE;
 412         mpe->mpe_length = sizeof(*mpe);
 413         mpe->mpe_busid = busid;
 414         mpe->mpe_address_modifier = address_modifier;
 415         mpe->mpe_range_list = range_list;
 416         smp_add_mpe_entry(mc, (mpe_t)mpe);
 417 }
 418
 419 void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa)
 420 {
 421         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE
 422                 | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
 423         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE
 424                 | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
 425 }
 426
 427 void mptable_add_isa_interrupts(struct mp_config_table *mc,
 428         unsigned long bus_isa, unsigned long apicid, int external_int2)
 429 {
 430 /*I/O Ints:                   Type         Trigger            Polarity
 431  *                                   Bus ID   IRQ  APIC ID   PIN# */
 432         smp_write_intsrc(mc, external_int2?mp_INT:mp_ExtINT,
 433                                      MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 434                                      bus_isa, 0x0, apicid, 0x0);
 435         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 436                                      bus_isa, 0x1, apicid, 0x1);
 437         smp_write_intsrc(mc, external_int2?mp_ExtINT:mp_INT,
 438                                      MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 439                                      bus_isa, 0x0, apicid, 0x2);
 440         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 441                                      bus_isa, 0x3, apicid, 0x3);
 442         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 443                                      bus_isa, 0x4, apicid, 0x4);
 444         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 445                                      bus_isa, 0x6, apicid, 0x6);
 446         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 447                                      bus_isa, 0x7, apicid, 0x7);
 448         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 449                                      bus_isa, 0x8, apicid, 0x8);
 450         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 451                                      bus_isa, 0x9, apicid, 0x9);
 452         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 453                                      bus_isa, 0xa, apicid, 0xa);
 454         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 455                                      bus_isa, 0xb, apicid, 0xb);
 456         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 457                                      bus_isa, 0xc, apicid, 0xc);
 458         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 459                                      bus_isa, 0xd, apicid, 0xd);
 460         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 461                                      bus_isa, 0xe, apicid, 0xe);
 462         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 463                                      bus_isa, 0xf, apicid, 0xf);
 464 }
 465
 466 void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus,
 467         int *isa_bus)
 468 {
 469         int dummy, i, highest;
 470         char buses[256];
 471         struct device *dev;
 472
 473         if (!max_pci_bus)
 474                 max_pci_bus = &dummy;
 475         if (!isa_bus)
 476                 isa_bus = &dummy;
 477
 478         *max_pci_bus = 0;
 479         highest = 0;
 480         memset(buses, 0, sizeof(buses));
 481
 482         for (dev = all_devices; dev; dev = dev->next) {
 483                 struct bus *bus;
 484                 for (bus = dev->link_list; bus; bus = bus->next) {
 485                         if (bus->secondary > 255) {
 486                                 printk(BIOS_ERR,
 487                                         "A bus claims to have a bus ID > 255?!? Aborting");
 488                                 return;
 489                         }
 490                         buses[bus->secondary] = 1;
 491                         if (highest < bus->secondary)
 492                                 highest = bus->secondary;
 493                 }
 494         }
 495         for (i = 0; i <= highest; i++) {
 496                 if (buses[i]) {
 497                         smp_write_bus(mc, i, "PCI   ");
 498                         *max_pci_bus = i;
 499                 }
 500         }
 501         *isa_bus = *max_pci_bus + 1;
 502         smp_write_bus(mc, *isa_bus, "ISA   ");
 503 }
 504
 505 void *mptable_finalize(struct mp_config_table *mc)
 506 {
 507         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
 508                 mc->mpe_length);
 509         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 510         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 511                 mc, smp_next_mpe_entry(mc));
 512         return smp_next_mpe_entry(mc);
 513 }
 514
 515 static const struct device *find_next_ioapic(unsigned int last_ioapic_id)
 516 {
 517         const struct device *dev;
 518         const struct device *result = NULL;
 519         unsigned int ioapic_id = MAX_APICS;
 520
 521         for (dev = all_devices; dev; dev = dev->next) {
 522                 if (dev->path.type == DEVICE_PATH_IOAPIC &&
 523                     dev->path.ioapic.ioapic_id > last_ioapic_id &&
 524                     dev->path.ioapic.ioapic_id <= ioapic_id) {
 525                         result = dev;
 526                 }
 527         }
 528         return result;
 529 }
 530
 531 unsigned long __weak write_smp_table(unsigned long addr)
 532 {
 533         struct drivers_generic_ioapic_config *ioapic_config;
 534         struct mp_config_table *mc;
 535         int isa_bus, pin, parentpin;
 536         const struct device *dev;
 537         const struct device *parent;
 538         const struct device *oldparent;
 539         void *tmp, *v;
 540         int isaioapic = -1, have_fixed_entries;
 541         const struct pci_irq_info *pci_irq_info;
 542         unsigned int ioapic_id = 0;
 543
 544         v = smp_write_floating_table(addr, 0);
 545         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 546
 547         mptable_init(mc);
 548
 549         smp_write_processors(mc);
 550
 551         mptable_write_buses(mc, NULL, &isa_bus);
 552
 553         while ((dev = find_next_ioapic(ioapic_id))) {
 554                 ioapic_config = dev->chip_info;
 555                 if (!ioapic_config) {
 556                         printk(BIOS_ERR, "%s has no config, ignoring\n",
 557                                 dev_path(dev));
 558                         ioapic_id++;
 559                         continue;
 560                 }
 561
 562                 ioapic_id = dev->path.ioapic.ioapic_id;
 563                 smp_write_ioapic(mc, ioapic_id,
 564                                      ioapic_config->version,
 565                                      ioapic_config->base);
 566
 567                 if (ioapic_config->have_isa_interrupts) {
 568                         if (isaioapic >= 0)
 569                                 printk(BIOS_ERR,
 570                                         "More than one IOAPIC with ISA interrupts?\n");
 571                         else
 572                                 isaioapic = dev->path.ioapic.ioapic_id;
 573                 }
 574         }
 575
 576         if (isaioapic >= 0) {
 577                 /* Legacy Interrupts */
 578                 printk(BIOS_DEBUG, "Writing ISA IRQs\n");
 579                 mptable_add_isa_interrupts(mc, isa_bus, isaioapic, 0);
 580         }
 581
 582         for (dev = all_devices; dev; dev = dev->next) {
 583
 584                 if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled)
 585                         continue;
 586
 587                 have_fixed_entries = 0;
 588                 for (pin = 0; pin < 4; pin++) {
 589                         if (dev->pci_irq_info[pin].ioapic_dst_id) {
 590                                 printk(BIOS_DEBUG,
 591                                         "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n",
 592                                                 dev_path(dev),
 593                                        pin + 'A',
 594                                        dev->pci_irq_info[pin].ioapic_dst_id,
 595                                        dev->pci_irq_info[pin].ioapic_irq_pin);
 596                                 smp_write_intsrc(mc, mp_INT,
 597                                          dev->pci_irq_info[pin].ioapic_flags,
 598                                          dev->bus->secondary,
 599                                          ((dev->path.pci.devfn & 0xf8) >> 1)
 600                                                 | pin,
 601                                          dev->pci_irq_info[pin].ioapic_dst_id,
 602                                          dev->pci_irq_info[pin].ioapic_irq_pin);
 603                                 have_fixed_entries = 1;
 604                         }
 605                 }
 606
 607                 if (!have_fixed_entries) {
 608                         pin = (dev->path.pci.devfn & 7) % 4;
 609                         oldparent = parent = dev;
 610                         while ((parent = parent->bus->dev)) {
 611                                 parentpin = (oldparent->path.pci.devfn >> 3)
 612                                         + (oldparent->path.pci.devfn & 7);
 613                                 parentpin += dev->path.pci.devfn & 7;
 614                                 parentpin += dev->path.pci.devfn >> 3;
 615                                 parentpin %= 4;
 616
 617                                 pci_irq_info = &parent->pci_irq_info[parentpin];
 618                                 if (pci_irq_info->ioapic_dst_id) {
 619                                         printk(BIOS_DEBUG,
 620                                                "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n",
 621                                                dev_path(dev), pin + 'A',
 622                                                pci_irq_info->ioapic_dst_id,
 623                                                pci_irq_info->ioapic_irq_pin);
 624                                         smp_write_intsrc(mc, mp_INT,
 625                                                  pci_irq_info->ioapic_flags,
 626                                                  dev->bus->secondary,
 627                                                  ((dev->path.pci.devfn & 0xf8)
 628                                                         >> 1) | pin,
 629                                                  pci_irq_info->ioapic_dst_id,
 630                                                  pci_irq_info->ioapic_irq_pin);
 631
 632                                         break;
 633                                 }
 634
 635                                 if (parent->path.type == DEVICE_PATH_DOMAIN) {
 636                                         printk(BIOS_WARNING,
 637                                                 "no IRQ found for %s\n",
 638                                                 dev_path(dev));
 639                                         break;
 640                                 }
 641                                 oldparent = parent;
 642                         }
 643                 }
 644         }
 645
 646         mptable_lintsrc(mc, isa_bus);
 647         tmp = mptable_finalize(mc);
 648         printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)((uintptr_t)tmp -
 649                                 (uintptr_t)v));
 650         return (unsigned long)tmp;
 651 }