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mb/google/skyrim: Enable Chrome EC
[coreboot.git] / src / arch / x86 / smbios.c
blobc48ce86c47e50f3e721aa97f73b7851bc13ee5b9
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <string.h>
5 #include <smbios.h>
6 #include <console/console.h>
7 #include <version.h>
8 #include <device/device.h>
9 #include <device/dram/spd.h>
10 #include <arch/cpu.h>
11 #include <cpu/x86/name.h>
12 #include <elog.h>
13 #include <endian.h>
14 #include <memory_info.h>
15 #include <spd.h>
16 #include <cbmem.h>
17 #include <commonlib/helpers.h>
18 #include <device/pci_ids.h>
19 #include <device/pci_def.h>
20 #include <device/pci.h>
21 #include <drivers/vpd/vpd.h>
22 #include <stdlib.h>
23
24 #define update_max(len, max_len, stmt) \
25 do { \
26 int tmp = stmt; \
27 \
28 max_len = MAX(max_len, tmp); \
29 len += tmp; \
30 } while (0)
31
32 static u8 smbios_checksum(u8 *p, u32 length)
33 {
34 u8 ret = 0;
35 while (length--)
36 ret += *p++;
37 return -ret;
38 }
39
40 int smbios_add_string(u8 *start, const char *str)
41 {
42 int i = 1;
43 char *p = (char *)start;
44
45 /*
46 * Return 0 as required for empty strings.
47 * See Section 6.1.3 "Text Strings" of the SMBIOS specification.
48 */
49 if (*str == '\0')
50 return 0;
51
52 for (;;) {
53 if (!*p) {
54 strcpy(p, str);
55 p += strlen(str);
56 *p++ = '\0';
57 *p++ = '\0';
58 return i;
59 }
60
61 if (!strcmp(p, str))
62 return i;
63
64 p += strlen(p)+1;
65 i++;
66 }
67 }
68
69 int smbios_string_table_len(u8 *start)
70 {
71 char *p = (char *)start;
72 int i, len = 0;
73
74 while (*p) {
75 i = strlen(p) + 1;
76 p += i;
77 len += i;
78 }
79
80 if (!len)
81 return 2;
82
83 return len + 1;
84 }
85
86 int smbios_full_table_len(struct smbios_header *header, u8 *str_table_start)
87 {
88 return header->length + smbios_string_table_len(str_table_start);
89 }
90
91 void *smbios_carve_table(unsigned long start, u8 type, u8 length, u16 handle)
92 {
93 struct smbios_header *t = (struct smbios_header *)start;
94
95 assert(length >= sizeof(*t));
96 memset(t, 0, length);
97 t->type = type;
98 t->length = length - 2;
99 t->handle = handle;
100 return t;
101 }
102
103 static int smbios_cpu_vendor(u8 *start)
104 {
105 if (cpu_have_cpuid()) {
106 u32 tmp[4];
107 const struct cpuid_result res = cpuid(0);
108 tmp[0] = res.ebx;
109 tmp[1] = res.edx;
110 tmp[2] = res.ecx;
111 tmp[3] = 0;
112 return smbios_add_string(start, (const char *)tmp);
113 } else {
114 return smbios_add_string(start, "Unknown");
115 }
116 }
117
118 static int smbios_processor_name(u8 *start)
119 {
120 u32 tmp[13];
121 const char *str = "Unknown Processor Name";
122 if (cpu_have_cpuid()) {
123 int i;
124 struct cpuid_result res = cpuid(0x80000000);
125 if (res.eax >= 0x80000004) {
126 int j = 0;
127 for (i = 0; i < 3; i++) {
128 res = cpuid(0x80000002 + i);
129 tmp[j++] = res.eax;
130 tmp[j++] = res.ebx;
131 tmp[j++] = res.ecx;
132 tmp[j++] = res.edx;
133 }
134 tmp[12] = 0;
135 str = (const char *)tmp;
136 }
137 }
138 return smbios_add_string(start, str);
139 }
140
141 /* this function will fill the corresponding manufacturer */
142 void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t)
143 {
144 const char *const manufacturer = spd_manufacturer_name(mod_id);
145
146 if (manufacturer) {
147 t->manufacturer = smbios_add_string(t->eos, manufacturer);
148 } else {
149 char string_buffer[256];
150
151 snprintf(string_buffer, sizeof(string_buffer), "Unknown (%x)", mod_id);
152 t->manufacturer = smbios_add_string(t->eos, string_buffer);
153 }
154 }
155
156 static void trim_trailing_whitespace(char *buffer, size_t buffer_size)
157 {
158 size_t len = strnlen(buffer, buffer_size);
159
160 if (len == 0)
161 return;
162
163 for (char *p = buffer + len - 1; p >= buffer; --p) {
164 if (*p == ' ')
165 *p = 0;
166 else
167 break;
168 }
169 }
170
171 /** This function will fill the corresponding part number */
172 static void smbios_fill_dimm_part_number(const char *part_number, struct smbios_type17 *t)
173 {
174 int invalid;
175 size_t i, len;
176 char trimmed_part_number[DIMM_INFO_PART_NUMBER_SIZE];
177
178 strncpy(trimmed_part_number, part_number, sizeof(trimmed_part_number));
179 trimmed_part_number[sizeof(trimmed_part_number) - 1] = '\0';
180
181 /*
182 * SPD mandates that unused characters be represented with a ' '.
183 * We don't want to publish the whitespace in the SMBIOS tables.
184 */
185 trim_trailing_whitespace(trimmed_part_number, sizeof(trimmed_part_number));
186
187 len = strlen(trimmed_part_number);
188
189 invalid = 0; /* assume valid */
190 for (i = 0; i < len; i++) {
191 if (trimmed_part_number[i] < ' ') {
192 invalid = 1;
193 trimmed_part_number[i] = '*';
194 }
195 }
196
197 if (len == 0) {
198 /* Null String in Part Number will have "None" instead. */
199 t->part_number = smbios_add_string(t->eos, "None");
200 } else if (invalid) {
201 char string_buffer[sizeof(trimmed_part_number) + 10];
202
203 snprintf(string_buffer, sizeof(string_buffer), "Invalid (%s)",
204 trimmed_part_number);
205 t->part_number = smbios_add_string(t->eos, string_buffer);
206 } else {
207 t->part_number = smbios_add_string(t->eos, trimmed_part_number);
208 }
209 }
210
211 /* Encodes the SPD serial number into hex */
212 static void smbios_fill_dimm_serial_number(const struct dimm_info *dimm,
213 struct smbios_type17 *t)
214 {
215 char serial[9];
216
217 snprintf(serial, sizeof(serial), "%02hhx%02hhx%02hhx%02hhx",
218 dimm->serial[0], dimm->serial[1], dimm->serial[2], dimm->serial[3]);
219
220 t->serial_number = smbios_add_string(t->eos, serial);
221 }
222
223 static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
224 unsigned long *current, int *handle,
225 int type16_handle)
226 {
227 struct spd_info info;
228 get_spd_info(dimm->ddr_type, dimm->mod_type, &info);
229
230 struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE,
231 sizeof(*t), *handle);
232
233 t->memory_type = dimm->ddr_type;
234 if (dimm->configured_speed_mts != 0)
235 t->clock_speed = dimm->configured_speed_mts;
236 else
237 t->clock_speed = dimm->ddr_frequency;
238 if (dimm->max_speed_mts != 0)
239 t->speed = dimm->max_speed_mts;
240 else
241 t->speed = dimm->ddr_frequency;
242 if (dimm->dimm_size < 0x7fff) {
243 t->size = dimm->dimm_size;
244 } else {
245 t->size = 0x7fff;
246 t->extended_size = dimm->dimm_size & 0x7fffffff;
247 }
248 t->data_width = 8 * (1 << (dimm->bus_width & 0x7));
249 t->total_width = t->data_width + 8 * ((dimm->bus_width & 0x18) >> 3);
250 t->form_factor = info.form_factor;
251
252 smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t);
253 smbios_fill_dimm_serial_number(dimm, t);
254 smbios_fill_dimm_asset_tag(dimm, t);
255 smbios_fill_dimm_locator(dimm, t);
256
257 /* put '\0' in the end of data */
258 dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0';
259 smbios_fill_dimm_part_number((char *)dimm->module_part_number, t);
260
261 /* Voltage Levels */
262 t->configured_voltage = dimm->vdd_voltage;
263 t->minimum_voltage = dimm->vdd_voltage;
264 t->maximum_voltage = dimm->vdd_voltage;
265
266 /* Fill in type detail */
267 t->type_detail = info.type_detail;
268
269 /* Synchronous = 1 */
270 t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS;
271 /* no handle for error information */
272 t->memory_error_information_handle = 0xFFFE;
273 t->attributes = dimm->rank_per_dimm;
274 t->phys_memory_array_handle = type16_handle;
275
276 *handle += 1;
277 return smbios_full_table_len(&t->header, t->eos);
278 }
279
280 #define VERSION_VPD "firmware_version"
281 static const char *vpd_get_bios_version(void)
282 {
283 int size;
284 const char *s;
285 char *version;
286
287 s = vpd_find(VERSION_VPD, &size, VPD_RO);
288 if (!s) {
289 printk(BIOS_ERR, "Find version from VPD %s failed\n", VERSION_VPD);
290 return NULL;
291 }
292
293 version = malloc(size + 1);
294 if (!version) {
295 printk(BIOS_ERR, "Failed to malloc %d bytes for VPD version\n", size + 1);
296 return NULL;
297 }
298 memcpy(version, s, size);
299 version[size] = '\0';
300 printk(BIOS_DEBUG, "Firmware version %s from VPD %s\n", version, VERSION_VPD);
301 return version;
302 }
303
304 static const char *get_bios_version(void)
305 {
306 const char *s;
307
308 #define SPACES \
309 " "
310
311 if (CONFIG(CHROMEOS))
312 return SPACES;
313
314 if (CONFIG(VPD_SMBIOS_VERSION)) {
315 s = vpd_get_bios_version();
316 if (s != NULL)
317 return s;
318 }
319
320 s = smbios_mainboard_bios_version();
321 if (s != NULL)
322 return s;
323
324 if (strlen(CONFIG_LOCALVERSION) != 0) {
325 printk(BIOS_DEBUG, "BIOS version set to CONFIG_LOCALVERSION: '%s'\n",
326 CONFIG_LOCALVERSION);
327 return CONFIG_LOCALVERSION;
328 }
329
330 printk(BIOS_DEBUG, "SMBIOS firmware version is set to coreboot_version: '%s'\n",
331 coreboot_version);
332 return coreboot_version;
333 }
334
335 static int smbios_write_type0(unsigned long *current, int handle)
336 {
337 struct smbios_type0 *t = smbios_carve_table(*current, SMBIOS_BIOS_INFORMATION,
338 sizeof(*t), handle);
339
340 t->vendor = smbios_add_string(t->eos, "coreboot");
341 t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
342
343 if (CONFIG(CHROMEOS_NVS)) {
344 uintptr_t version_address = (uintptr_t)t->eos;
345 /* SMBIOS offsets start at 1 rather than 0 */
346 version_address += (u32)smbios_string_table_len(t->eos) - 1;
347 smbios_type0_bios_version(version_address);
348 }
349 t->bios_version = smbios_add_string(t->eos, get_bios_version());
350 uint32_t rom_size = CONFIG_ROM_SIZE;
351 rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB);
352 t->bios_rom_size = (rom_size / 65535) - 1;
353
354 if (CONFIG_ROM_SIZE >= 1 * GiB) {
355 t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, GiB) | (1 << 14);
356 } else {
357 t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, MiB);
358 }
359
360 t->system_bios_major_release = coreboot_major_revision;
361 t->system_bios_minor_release = coreboot_minor_revision;
362
363 smbios_ec_revision(&t->ec_major_release, &t->ec_minor_release);
364
365 t->bios_characteristics =
366 BIOS_CHARACTERISTICS_PCI_SUPPORTED |
367 BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
368 BIOS_CHARACTERISTICS_UPGRADEABLE;
369
370 if (CONFIG(CARDBUS_PLUGIN_SUPPORT))
371 t->bios_characteristics |= BIOS_CHARACTERISTICS_PC_CARD;
372
373 if (CONFIG(HAVE_ACPI_TABLES))
374 t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
375
376 t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;
377 const int len = smbios_full_table_len(&t->header, t->eos);
378 *current += len;
379 return len;
380 }
381
382 static int get_socket_type(void)
383 {
384 if (CONFIG(CPU_INTEL_SLOT_1))
385 return 0x08;
386 if (CONFIG(CPU_INTEL_SOCKET_MPGA604))
387 return 0x13;
388 if (CONFIG(CPU_INTEL_SOCKET_LGA775))
389 return 0x15;
390 if (CONFIG(XEON_SP_COMMON_BASE))
391 return 0x36;
392
393 return 0x02; /* Unknown */
394 }
395
396 unsigned int __weak smbios_processor_external_clock(void)
397 {
398 return 0; /* Unknown */
399 }
400
401 unsigned int __weak smbios_processor_characteristics(void)
402 {
403 return 0;
404 }
405
406 unsigned int __weak smbios_processor_family(struct cpuid_result res)
407 {
408 return (res.eax > 0) ? 0x0c : 0x6;
409 }
410
411 unsigned int __weak smbios_cache_error_correction_type(u8 level)
412 {
413 return SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN;
414 }
415
416 unsigned int __weak smbios_cache_sram_type(void)
417 {
418 return SMBIOS_CACHE_SRAM_TYPE_UNKNOWN;
419 }
420
421 unsigned int __weak smbios_cache_conf_operation_mode(u8 level)
422 {
423 return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */
424 }
425
426 /* Returns the processor voltage in 100mV units */
427 unsigned int __weak smbios_cpu_get_voltage(void)
428 {
429 return 0; /* Unknown */
430 }
431
432 static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache)
433 {
434 size_t number_of_cpus_per_package = 0;
435 size_t max_logical_cpus_per_package = 0;
436 struct cpuid_result res;
437
438 if (!cpu_have_cpuid())
439 return 1;
440
441 res = cpuid(1);
442
443 max_logical_cpus_per_package = (res.ebx >> 16) & 0xff;
444
445 /* Check if it's last level cache */
446 if (max_logical_cpus_sharing_cache == max_logical_cpus_per_package)
447 return 1;
448
449 if (cpuid_get_max_func() >= 0xb) {
450 res = cpuid_ext(0xb, 1);
451 number_of_cpus_per_package = res.ebx & 0xff;
452 } else {
453 number_of_cpus_per_package = max_logical_cpus_per_package;
454 }
455
456 return number_of_cpus_per_package / max_logical_cpus_sharing_cache;
457 }
458
459 static int smbios_write_type1(unsigned long *current, int handle)
460 {
461 struct smbios_type1 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_INFORMATION,
462 sizeof(*t), handle);
463
464 t->manufacturer = smbios_add_string(t->eos, smbios_system_manufacturer());
465 t->product_name = smbios_add_string(t->eos, smbios_system_product_name());
466 t->serial_number = smbios_add_string(t->eos, smbios_system_serial_number());
467 t->wakeup_type = smbios_system_wakeup_type();
468 t->sku = smbios_add_string(t->eos, smbios_system_sku());
469 t->version = smbios_add_string(t->eos, smbios_system_version());
470 #ifdef CONFIG_MAINBOARD_FAMILY
471 t->family = smbios_add_string(t->eos, CONFIG_MAINBOARD_FAMILY);
472 #endif
473 smbios_system_set_uuid(t->uuid);
474 const int len = smbios_full_table_len(&t->header, t->eos);
475 *current += len;
476 return len;
477 }
478
479 static int smbios_write_type2(unsigned long *current, int handle, const int chassis_handle)
480 {
481 struct smbios_type2 *t = smbios_carve_table(*current, SMBIOS_BOARD_INFORMATION,
482 sizeof(*t), handle);
483
484 t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer());
485 t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name());
486 t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number());
487 t->version = smbios_add_string(t->eos, smbios_mainboard_version());
488 t->asset_tag = smbios_add_string(t->eos, smbios_mainboard_asset_tag());
489 t->feature_flags = smbios_mainboard_feature_flags();
490 t->location_in_chassis = smbios_add_string(t->eos,
491 smbios_mainboard_location_in_chassis());
492 t->board_type = smbios_mainboard_board_type();
493 t->chassis_handle = chassis_handle;
494 const int len = smbios_full_table_len(&t->header, t->eos);
495 *current += len;
496 return len;
497 }
498
499 static int smbios_write_type3(unsigned long *current, int handle)
500 {
501 struct smbios_type3 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_ENCLOSURE,
502 sizeof(*t), handle);
503
504 t->manufacturer = smbios_add_string(t->eos, smbios_system_manufacturer());
505 t->bootup_state = SMBIOS_STATE_SAFE;
506 t->power_supply_state = SMBIOS_STATE_SAFE;
507 t->thermal_state = SMBIOS_STATE_SAFE;
508 t->_type = smbios_mainboard_enclosure_type();
509 t->security_status = SMBIOS_STATE_SAFE;
510 t->number_of_power_cords = smbios_chassis_power_cords();
511 t->asset_tag_number = smbios_add_string(t->eos, smbios_mainboard_asset_tag());
512 t->version = smbios_add_string(t->eos, smbios_chassis_version());
513 t->serial_number = smbios_add_string(t->eos, smbios_chassis_serial_number());
514 const int len = smbios_full_table_len(&t->header, t->eos);
515 *current += len;
516 return len;
517 }
518
519 static int smbios_write_type4(unsigned long *current, int handle)
520 {
521 unsigned int cpu_voltage;
522 struct cpuid_result res;
523 uint16_t characteristics = 0;
524 static unsigned int cnt = 0;
525 char buf[8];
526
527 /* Provide sane defaults even for CPU without CPUID */
528 res.eax = res.edx = 0;
529 res.ebx = 0x10000;
530
531 if (cpu_have_cpuid())
532 res = cpuid(1);
533
534 struct smbios_type4 *t = smbios_carve_table(*current, SMBIOS_PROCESSOR_INFORMATION,
535 sizeof(*t), handle);
536
537 snprintf(buf, sizeof(buf), "CPU%d", cnt++);
538 t->socket_designation = smbios_add_string(t->eos, buf);
539
540 t->processor_id[0] = res.eax;
541 t->processor_id[1] = res.edx;
542 t->processor_manufacturer = smbios_cpu_vendor(t->eos);
543 t->processor_version = smbios_processor_name(t->eos);
544 t->processor_family = smbios_processor_family(res);
545 t->processor_type = 3; /* System Processor */
546 /*
547 * If CPUID leaf 11 is available, calculate "core count" by dividing
548 * SMT_ID (logical processors in a core) by Core_ID (number of cores).
549 * This seems to be the way to arrive to a number of cores mentioned on
550 * ark.intel.com.
551 */
552 if (cpu_have_cpuid() && cpuid_get_max_func() >= 0xb) {
553 uint32_t leaf_b_cores = 0, leaf_b_threads = 0;
554 res = cpuid_ext(0xb, 1);
555 leaf_b_cores = res.ebx;
556 res = cpuid_ext(0xb, 0);
557 leaf_b_threads = res.ebx;
558 /* if hyperthreading is not available, pretend this is 1 */
559 if (leaf_b_threads == 0) {
560 leaf_b_threads = 1;
561 }
562 t->core_count2 = leaf_b_cores / leaf_b_threads;
563 t->core_count = t->core_count2 > 0xff ? 0xff : t->core_count2;
564 t->thread_count2 = leaf_b_cores;
565 t->thread_count = t->thread_count2 > 0xff ? 0xff : t->thread_count2;
566 } else {
567 t->core_count = (res.ebx >> 16) & 0xff;
568 t->core_count2 = t->core_count;
569 t->thread_count2 = t->core_count2;
570 t->thread_count = t->thread_count2;
571 }
572 /* Assume we enable all the cores always, capped only by MAX_CPUS */
573 t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS);
574 t->core_enabled2 = MIN(t->core_count2, CONFIG_MAX_CPUS);
575 t->l1_cache_handle = 0xffff;
576 t->l2_cache_handle = 0xffff;
577 t->l3_cache_handle = 0xffff;
578 t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number());
579 t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED;
580 t->processor_upgrade = get_socket_type();
581 if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) {
582 t->current_speed = cpuid_eax(0x16); /* base frequency */
583 t->external_clock = cpuid_ecx(0x16);
584 } else {
585 t->current_speed = smbios_cpu_get_current_speed_mhz();
586 t->external_clock = smbios_processor_external_clock();
587 }
588
589 /* This field identifies a capability for the system, not the processor itself. */
590 t->max_speed = smbios_cpu_get_max_speed_mhz();
591
592 if (cpu_have_cpuid()) {
593 res = cpuid(1);
594
595 if ((res.ecx) & BIT(5))
596 characteristics |= BIT(6); /* BIT6: Enhanced Virtualization */
597
598 if ((res.edx) & BIT(28))
599 characteristics |= BIT(4); /* BIT4: Hardware Thread */
600
601 if (((cpuid_eax(0x80000000) - 0x80000000) + 1) > 2) {
602 res = cpuid(0x80000001);
603
604 if ((res.edx) & BIT(20))
605 characteristics |= BIT(5); /* BIT5: Execute Protection */
606 }
607 }
608 t->processor_characteristics = characteristics | smbios_processor_characteristics();
609 cpu_voltage = smbios_cpu_get_voltage();
610 if (cpu_voltage > 0)
611 t->voltage = 0x80 | cpu_voltage;
612
613 const int len = smbios_full_table_len(&t->header, t->eos);
614 *current += len;
615 return len;
616 }
617
618 /*
619 * Write SMBIOS type 7.
620 * Fill in some fields with constant values, as gathering the information
621 * from CPUID is impossible.
622 */
623 static int smbios_write_type7(unsigned long *current,
624 const int handle,
625 const u8 level,
626 const u8 sram_type,
627 const enum smbios_cache_associativity associativity,
628 const enum smbios_cache_type type,
629 const size_t max_cache_size,
630 const size_t cache_size)
631 {
632 char buf[8];
633
634 struct smbios_type7 *t = smbios_carve_table(*current, SMBIOS_CACHE_INFORMATION,
635 sizeof(*t), handle);
636
637 snprintf(buf, sizeof(buf), "CACHE%x", level);
638 t->socket_designation = smbios_add_string(t->eos, buf);
639
640 t->cache_configuration = SMBIOS_CACHE_CONF_LEVEL(level) |
641 SMBIOS_CACHE_CONF_LOCATION(0) | /* Internal */
642 SMBIOS_CACHE_CONF_ENABLED(1) | /* Enabled */
643 SMBIOS_CACHE_CONF_OPERATION_MODE(smbios_cache_conf_operation_mode(level));
644
645 if (max_cache_size < (SMBIOS_CACHE_SIZE_MASK * KiB)) {
646 t->max_cache_size = max_cache_size / KiB;
647 t->max_cache_size2 = t->max_cache_size;
648
649 t->max_cache_size |= SMBIOS_CACHE_SIZE_UNIT_1KB;
650 t->max_cache_size2 |= SMBIOS_CACHE_SIZE2_UNIT_1KB;
651 } else {
652 if (max_cache_size < (SMBIOS_CACHE_SIZE_MASK * 64 * KiB))
653 t->max_cache_size = max_cache_size / (64 * KiB);
654 else
655 t->max_cache_size = SMBIOS_CACHE_SIZE_OVERFLOW;
656 t->max_cache_size2 = max_cache_size / (64 * KiB);
657
658 t->max_cache_size |= SMBIOS_CACHE_SIZE_UNIT_64KB;
659 t->max_cache_size2 |= SMBIOS_CACHE_SIZE2_UNIT_64KB;
660 }
661
662 if (cache_size < (SMBIOS_CACHE_SIZE_MASK * KiB)) {
663 t->installed_size = cache_size / KiB;
664 t->installed_size2 = t->installed_size;
665
666 t->installed_size |= SMBIOS_CACHE_SIZE_UNIT_1KB;
667 t->installed_size2 |= SMBIOS_CACHE_SIZE2_UNIT_1KB;
668 } else {
669 if (cache_size < (SMBIOS_CACHE_SIZE_MASK * 64 * KiB))
670 t->installed_size = cache_size / (64 * KiB);
671 else
672 t->installed_size = SMBIOS_CACHE_SIZE_OVERFLOW;
673 t->installed_size2 = cache_size / (64 * KiB);
674
675 t->installed_size |= SMBIOS_CACHE_SIZE_UNIT_64KB;
676 t->installed_size2 |= SMBIOS_CACHE_SIZE2_UNIT_64KB;
677 }
678
679 t->associativity = associativity;
680 t->supported_sram_type = sram_type;
681 t->current_sram_type = sram_type;
682 t->cache_speed = 0; /* Unknown */
683 t->error_correction_type = smbios_cache_error_correction_type(level);
684 t->system_cache_type = type;
685
686 const int len = smbios_full_table_len(&t->header, t->eos);
687 *current += len;
688 return len;
689 }
690
691 /* Convert the associativity as integer to the SMBIOS enum if available */
692 static enum smbios_cache_associativity smbios_cache_associativity(const u8 num)
693 {
694 switch (num) {
695 case 1:
696 return SMBIOS_CACHE_ASSOCIATIVITY_DIRECT;
697 case 2:
698 return SMBIOS_CACHE_ASSOCIATIVITY_2WAY;
699 case 4:
700 return SMBIOS_CACHE_ASSOCIATIVITY_4WAY;
701 case 8:
702 return SMBIOS_CACHE_ASSOCIATIVITY_8WAY;
703 case 12:
704 return SMBIOS_CACHE_ASSOCIATIVITY_12WAY;
705 case 16:
706 return SMBIOS_CACHE_ASSOCIATIVITY_16WAY;
707 case 20:
708 return SMBIOS_CACHE_ASSOCIATIVITY_20WAY;
709 case 24:
710 return SMBIOS_CACHE_ASSOCIATIVITY_24WAY;
711 case 32:
712 return SMBIOS_CACHE_ASSOCIATIVITY_32WAY;
713 case 48:
714 return SMBIOS_CACHE_ASSOCIATIVITY_48WAY;
715 case 64:
716 return SMBIOS_CACHE_ASSOCIATIVITY_64WAY;
717 case 0xff:
718 return SMBIOS_CACHE_ASSOCIATIVITY_FULL;
719 default:
720 return SMBIOS_CACHE_ASSOCIATIVITY_UNKNOWN;
721 };
722 }
723
724 /*
725 * Parse the "Deterministic Cache Parameters" as provided by Intel in
726 * leaf 4 or AMD in extended leaf 0x8000001d.
727 *
728 * @param current Pointer to memory address to write the tables to
729 * @param handle Pointer to handle for the tables
730 * @param max_struct_size Pointer to maximum struct size
731 * @param type4 Pointer to SMBIOS type 4 structure
732 */
733 static int smbios_write_type7_cache_parameters(unsigned long *current,
734 int *handle,
735 int *max_struct_size,
736 struct smbios_type4 *type4)
737 {
738 unsigned int cnt = CACHE_L1D;
739 int len = 0;
740
741 if (!cpu_have_cpuid())
742 return len;
743
744 enum cpu_type dcache_cpuid = cpu_check_deterministic_cache_cpuid_supported();
745 if (dcache_cpuid == CPUID_TYPE_INVALID || dcache_cpuid == CPUID_COMMAND_UNSUPPORTED) {
746 printk(BIOS_DEBUG, "SMBIOS: Unknown CPU or CPU doesn't support Deterministic "
747 "Cache CPUID leaf\n");
748 return len;
749 }
750
751 while (1) {
752 enum smbios_cache_associativity associativity;
753 enum smbios_cache_type type;
754 struct cpu_cache_info info;
755 if (!fill_cpu_cache_info(cnt++, &info))
756 continue;
757
758 const u8 cache_type = info.type;
759 const u8 level = info.level;
760 const size_t assoc = info.num_ways;
761 const size_t cache_share = info.num_cores_shared;
762 const size_t cache_size = info.size * get_number_of_caches(cache_share);
763
764 if (!cache_type)
765 /* No more caches in the system */
766 break;
767
768 switch (cache_type) {
769 case 1:
770 type = SMBIOS_CACHE_TYPE_DATA;
771 break;
772 case 2:
773 type = SMBIOS_CACHE_TYPE_INSTRUCTION;
774 break;
775 case 3:
776 type = SMBIOS_CACHE_TYPE_UNIFIED;
777 break;
778 default:
779 type = SMBIOS_CACHE_TYPE_UNKNOWN;
780 break;
781 }
782
783 if (info.fully_associative)
784 associativity = SMBIOS_CACHE_ASSOCIATIVITY_FULL;
785 else
786 associativity = smbios_cache_associativity(assoc);
787
788 const int h = (*handle)++;
789
790 update_max(len, *max_struct_size, smbios_write_type7(current, h,
791 level, smbios_cache_sram_type(), associativity,
792 type, cache_size, cache_size));
793
794 if (type4) {
795 switch (level) {
796 case 1:
797 type4->l1_cache_handle = h;
798 break;
799 case 2:
800 type4->l2_cache_handle = h;
801 break;
802 case 3:
803 type4->l3_cache_handle = h;
804 break;
805 }
806 }
807 };
808
809 return len;
810 }
811
812 int smbios_write_type8(unsigned long *current, int *handle,
813 const struct port_information *port,
814 size_t num_ports)
815 {
816 unsigned int totallen = 0, i;
817
818 for (i = 0; i < num_ports; i++, port++) {
819 struct smbios_type8 *t = smbios_carve_table(*current,
820 SMBIOS_PORT_CONNECTOR_INFORMATION,
821 sizeof(*t), *handle);
822 t->internal_reference_designator =
823 smbios_add_string(t->eos, port->internal_reference_designator);
824 t->internal_connector_type = port->internal_connector_type;
825 t->external_reference_designator =
826 smbios_add_string(t->eos, port->external_reference_designator);
827 t->external_connector_type = port->external_connector_type;
828 t->port_type = port->port_type;
829 *handle += 1;
830 const int len = smbios_full_table_len(&t->header, t->eos);
831 *current += len;
832 totallen += len;
833 }
834 return totallen;
835 }
836
837 int smbios_write_type9(unsigned long *current, int *handle,
838 const char *name, const enum misc_slot_type type,
839 const enum slot_data_bus_bandwidth bandwidth,
840 const enum misc_slot_usage usage,
841 const enum misc_slot_length length,
842 const u16 id, u8 slot_char1, u8 slot_char2, u8 bus, u8 dev_func)
843 {
844 struct smbios_type9 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_SLOTS,
845 sizeof(*t), *handle);
846
847 t->slot_designation = smbios_add_string(t->eos, name ? name : "SLOT");
848 t->slot_type = type;
849 /* TODO add slot_id supoort, will be "_SUN" for ACPI devices */
850 t->slot_id = id;
851 t->slot_data_bus_width = bandwidth;
852 t->current_usage = usage;
853 t->slot_length = length;
854 t->slot_characteristics_1 = slot_char1;
855 t->slot_characteristics_2 = slot_char2;
856 t->segment_group_number = 0;
857 t->bus_number = bus;
858 t->device_function_number = dev_func;
859 t->data_bus_width = SlotDataBusWidthOther;
860
861 const int len = smbios_full_table_len(&t->header, t->eos);
862 *current += len;
863 *handle += 1;
864 return len;
865 }
866
867 static int smbios_write_type11(unsigned long *current, int *handle)
868 {
869 struct device *dev;
870 struct smbios_type11 *t = smbios_carve_table(*current, SMBIOS_OEM_STRINGS,
871 sizeof(*t), *handle);
872
873 for (dev = all_devices; dev; dev = dev->next) {
874 if (dev->ops && dev->ops->get_smbios_strings)
875 dev->ops->get_smbios_strings(dev, t);
876 }
877
878 if (t->count == 0) {
879 memset(t, 0, sizeof(*t));
880 return 0;
881 }
882
883 const int len = smbios_full_table_len(&t->header, t->eos);
884 *current += len;
885 (*handle)++;
886 return len;
887 }
888
889 static int smbios_write_type16(unsigned long *current, int *handle)
890 {
891 int i;
892 uint64_t max_capacity;
893
894 struct memory_info *meminfo;
895 meminfo = cbmem_find(CBMEM_ID_MEMINFO);
896 if (meminfo == NULL)
897 return 0; /* can't find mem info in cbmem */
898
899 printk(BIOS_INFO, "Create SMBIOS type 16\n");
900
901 if (meminfo->max_capacity_mib == 0 || meminfo->number_of_devices == 0) {
902 /* Fill in defaults if not provided */
903 meminfo->number_of_devices = 0;
904 meminfo->max_capacity_mib = 0;
905 for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) {
906 meminfo->max_capacity_mib += meminfo->dimm[i].dimm_size;
907 meminfo->number_of_devices += !!meminfo->dimm[i].dimm_size;
908 }
909 }
910
911 struct smbios_type16 *t = smbios_carve_table(*current, SMBIOS_PHYS_MEMORY_ARRAY,
912 sizeof(*t), *handle);
913
914 t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
915 t->use = MEMORY_ARRAY_USE_SYSTEM;
916 t->memory_error_correction = meminfo->ecc_type;
917
918 /* no error information handle available */
919 t->memory_error_information_handle = 0xFFFE;
920 max_capacity = meminfo->max_capacity_mib;
921 if (max_capacity * (MiB / KiB) < SMBIOS_USE_EXTENDED_MAX_CAPACITY)
922 t->maximum_capacity = max_capacity * (MiB / KiB);
923 else {
924 t->maximum_capacity = SMBIOS_USE_EXTENDED_MAX_CAPACITY;
925 t->extended_maximum_capacity = max_capacity * MiB;
926 }
927 t->number_of_memory_devices = meminfo->number_of_devices;
928
929 const int len = smbios_full_table_len(&t->header, t->eos);
930 *current += len;
931 (*handle)++;
932 return len;
933 }
934
935 static int smbios_write_type17(unsigned long *current, int *handle, int type16)
936 {
937 int totallen = 0;
938 int i;
939
940 struct memory_info *meminfo;
941 meminfo = cbmem_find(CBMEM_ID_MEMINFO);
942 if (meminfo == NULL)
943 return 0; /* can't find mem info in cbmem */
944
945 printk(BIOS_INFO, "Create SMBIOS type 17\n");
946 for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) {
947 struct dimm_info *dimm;
948 dimm = &meminfo->dimm[i];
949 /*
950 * Windows 10 GetPhysicallyInstalledSystemMemory functions reads SMBIOS tables
951 * type 16 and type 17. The type 17 tables need to point to a type 16 table.
952 * Otherwise, the physical installed memory size is guessed from the system
953 * memory map, which results in a slightly smaller value than the actual size.
954 */
955 const int len = create_smbios_type17_for_dimm(dimm, current, handle, type16);
956 *current += len;
957 totallen += len;
958 }
959 return totallen;
960 }
961
962 static int smbios_write_type19(unsigned long *current, int *handle, int type16)
963 {
964 int i;
965
966 struct memory_info *meminfo;
967 meminfo = cbmem_find(CBMEM_ID_MEMINFO);
968 if (meminfo == NULL)
969 return 0; /* can't find mem info in cbmem */
970
971 struct smbios_type19 *t = smbios_carve_table(*current,
972 SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS,
973 sizeof(*t), *handle);
974
975 t->memory_array_handle = type16;
976
977 for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) {
978 if (meminfo->dimm[i].dimm_size > 0) {
979 t->extended_ending_address += meminfo->dimm[i].dimm_size;
980 t->partition_width++;
981 }
982 }
983 t->extended_ending_address *= MiB;
984
985 /* Check if it fits into regular address */
986 if (t->extended_ending_address >= KiB &&
987 t->extended_ending_address < 0x40000000000ULL) {
988 /*
989 * FIXME: The starting address is SoC specific, but SMBIOS tables are only
990 * exported on x86 where it's always 0.
991 */
992
993 t->starting_address = 0;
994 t->ending_address = t->extended_ending_address / KiB - 1;
995 t->extended_starting_address = ~0;
996 t->extended_ending_address = ~0;
997 } else {
998 t->starting_address = ~0;
999 t->ending_address = ~0;
1000 t->extended_starting_address = 0;
1001 t->extended_ending_address--;
1002 }
1003
1004 const int len = smbios_full_table_len(&t->header, t->eos);
1005 *current += len;
1006 *handle += 1;
1007 return len;
1008 }
1009
1010 static int smbios_write_type20_table(unsigned long *current, int *handle, u32 addr_start,
1011 u32 addr_end, int type17_handle, int type19_handle)
1012 {
1013 struct smbios_type20 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS,
1014 sizeof(*t), *handle);
1015
1016 t->memory_device_handle = type17_handle;
1017 t->memory_array_mapped_address_handle = type19_handle;
1018 t->addr_start = addr_start;
1019 t->addr_end = addr_end;
1020 t->partition_row_pos = 0xff;
1021 t->interleave_pos = 0xff;
1022 t->interleave_depth = 0xff;
1023
1024 const int len = smbios_full_table_len(&t->header, t->eos);
1025 *current += len;
1026 *handle += 1;
1027 return len;
1028 }
1029
1030 static int smbios_write_type20(unsigned long *current, int *handle,
1031 int type17_handle, int type19_handle)
1032 {
1033 u32 start_addr = 0;
1034 int totallen = 0;
1035 int i;
1036
1037 struct memory_info *meminfo;
1038 meminfo = cbmem_find(CBMEM_ID_MEMINFO);
1039 if (meminfo == NULL)
1040 return 0; /* can't find mem info in cbmem */
1041
1042 printk(BIOS_INFO, "Create SMBIOS type 20\n");
1043 for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) {
1044 struct dimm_info *dimm;
1045 dimm = &meminfo->dimm[i];
1046 u32 end_addr = start_addr + (dimm->dimm_size << 10) - 1;
1047 totallen += smbios_write_type20_table(current, handle, start_addr, end_addr,
1048 type17_handle, type19_handle);
1049 start_addr = end_addr + 1;
1050 }
1051 return totallen;
1052 }
1053
1054 static int smbios_write_type32(unsigned long *current, int handle)
1055 {
1056 struct smbios_type32 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_BOOT_INFORMATION,
1057 sizeof(*t), handle);
1058
1059 const int len = smbios_full_table_len(&t->header, t->eos);
1060 *current += len;
1061 return len;
1062 }
1063
1064 int smbios_write_type38(unsigned long *current, int *handle,
1065 const enum smbios_bmc_interface_type interface_type,
1066 const u8 ipmi_rev, const u8 i2c_addr, const u8 nv_addr,
1067 const u64 base_addr, const u8 base_modifier,
1068 const u8 irq)
1069 {
1070 struct smbios_type38 *t = smbios_carve_table(*current, SMBIOS_IPMI_DEVICE_INFORMATION,
1071 sizeof(*t), *handle);
1072
1073 t->interface_type = interface_type;
1074 t->ipmi_rev = ipmi_rev;
1075 t->i2c_slave_addr = i2c_addr;
1076 t->nv_storage_addr = nv_addr;
1077 t->base_address = base_addr;
1078 t->base_address_modifier = base_modifier;
1079 t->irq = irq;
1080
1081 const int len = smbios_full_table_len(&t->header, t->eos);
1082 *current += len;
1083 *handle += 1;
1084 return len;
1085 }
1086
1087 int smbios_write_type41(unsigned long *current, int *handle,
1088 const char *name, u8 instance, u16 segment,
1089 u8 bus, u8 device, u8 function, u8 device_type)
1090 {
1091 struct smbios_type41 *t = smbios_carve_table(*current,
1092 SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION,
1093 sizeof(*t), *handle);
1094
1095 t->reference_designation = smbios_add_string(t->eos, name);
1096 t->device_type = device_type;
1097 t->device_status = 1;
1098 t->device_type_instance = instance;
1099 t->segment_group_number = segment;
1100 t->bus_number = bus;
1101 t->device_number = device;
1102 t->function_number = function;
1103
1104 const int len = smbios_full_table_len(&t->header, t->eos);
1105 *current += len;
1106 *handle += 1;
1107 return len;
1108 }
1109
1110 static int smbios_write_type127(unsigned long *current, int handle)
1111 {
1112 struct smbios_type127 *t = smbios_carve_table(*current, SMBIOS_END_OF_TABLE,
1113 sizeof(*t), handle);
1114
1115 const int len = smbios_full_table_len(&t->header, t->eos);
1116 *current += len;
1117 return len;
1118 }
1119
1120 /* Get the device type 41 from the dev struct */
1121 static u8 smbios_get_device_type_from_dev(struct device *dev)
1122 {
1123 u16 pci_basesubclass = (dev->class >> 8) & 0xFFFF;
1124
1125 switch (pci_basesubclass) {
1126 case PCI_CLASS_NOT_DEFINED:
1127 return SMBIOS_DEVICE_TYPE_OTHER;
1128 case PCI_CLASS_DISPLAY_VGA:
1129 case PCI_CLASS_DISPLAY_XGA:
1130 case PCI_CLASS_DISPLAY_3D:
1131 case PCI_CLASS_DISPLAY_OTHER:
1132 return SMBIOS_DEVICE_TYPE_VIDEO;
1133 case PCI_CLASS_STORAGE_SCSI:
1134 return SMBIOS_DEVICE_TYPE_SCSI;
1135 case PCI_CLASS_NETWORK_ETHERNET:
1136 return SMBIOS_DEVICE_TYPE_ETHERNET;
1137 case PCI_CLASS_NETWORK_TOKEN_RING:
1138 return SMBIOS_DEVICE_TYPE_TOKEN_RING;
1139 case PCI_CLASS_MULTIMEDIA_VIDEO:
1140 case PCI_CLASS_MULTIMEDIA_AUDIO:
1141 case PCI_CLASS_MULTIMEDIA_PHONE:
1142 case PCI_CLASS_MULTIMEDIA_OTHER:
1143 return SMBIOS_DEVICE_TYPE_SOUND;
1144 case PCI_CLASS_STORAGE_ATA:
1145 return SMBIOS_DEVICE_TYPE_PATA;
1146 case PCI_CLASS_STORAGE_SATA:
1147 return SMBIOS_DEVICE_TYPE_SATA;
1148 case PCI_CLASS_STORAGE_SAS:
1149 return SMBIOS_DEVICE_TYPE_SAS;
1150 default:
1151 return SMBIOS_DEVICE_TYPE_UNKNOWN;
1152 }
1153 }
1154
1155 static bool smbios_get_type41_instance_id(struct device *dev, u8 device_type, u8 *instance_id)
1156 {
1157 #if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
1158 *instance_id = dev->smbios_instance_id;
1159 return dev->smbios_instance_id_valid;
1160 #else
1161 static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {};
1162
1163 if (device_type == SMBIOS_DEVICE_TYPE_OTHER ||
1164 device_type == SMBIOS_DEVICE_TYPE_UNKNOWN)
1165 return false;
1166
1167 if (device_type > SMBIOS_DEVICE_TYPE_COUNT)
1168 return false;
1169
1170 *instance_id = type41_inst_cnt[device_type]++;
1171 return true;
1172 #endif
1173 }
1174
1175 static const char *smbios_get_type41_refdes(struct device *dev)
1176 {
1177 #if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
1178 if (dev->smbios_refdes)
1179 return dev->smbios_refdes;
1180 #endif
1181 return get_pci_subclass_name(dev);
1182 }
1183
1184 static int smbios_generate_type41_from_devtree(struct device *dev, int *handle,
1185 unsigned long *current)
1186 {
1187 if (dev->path.type != DEVICE_PATH_PCI)
1188 return 0;
1189 if (!dev->on_mainboard)
1190 return 0;
1191
1192 const u8 device_type = smbios_get_device_type_from_dev(dev);
1193
1194 u8 instance_id;
1195
1196 if (!smbios_get_type41_instance_id(dev, device_type, &instance_id))
1197 return 0;
1198
1199 const char *name = smbios_get_type41_refdes(dev);
1200
1201 return smbios_write_type41(current, handle,
1202 name, // name
1203 instance_id, // inst
1204 0, // segment
1205 dev->bus->secondary, //bus
1206 PCI_SLOT(dev->path.pci.devfn), // device
1207 PCI_FUNC(dev->path.pci.devfn), // func
1208 device_type);
1209 }
1210
1211 static int smbios_generate_type9_from_devtree(struct device *dev, int *handle,
1212 unsigned long *current)
1213 {
1214 enum misc_slot_usage usage;
1215 enum slot_data_bus_bandwidth bandwidth;
1216 enum misc_slot_type type;
1217 enum misc_slot_length length;
1218
1219 if (dev->path.type != DEVICE_PATH_PCI)
1220 return 0;
1221
1222 if (!dev->smbios_slot_type && !dev->smbios_slot_data_width &&
1223 !dev->smbios_slot_designation && !dev->smbios_slot_length)
1224 return 0;
1225
1226 if (dev_is_active_bridge(dev))
1227 usage = SlotUsageInUse;
1228 else if (dev->enabled)
1229 usage = SlotUsageAvailable;
1230 else
1231 usage = SlotUsageUnknown;
1232
1233 if (dev->smbios_slot_data_width)
1234 bandwidth = dev->smbios_slot_data_width;
1235 else
1236 bandwidth = SlotDataBusWidthUnknown;
1237
1238 if (dev->smbios_slot_type)
1239 type = dev->smbios_slot_type;
1240 else
1241 type = SlotTypeUnknown;
1242
1243 if (dev->smbios_slot_length)
1244 length = dev->smbios_slot_length;
1245 else
1246 length = SlotLengthUnknown;
1247
1248 return smbios_write_type9(current, handle,
1249 dev->smbios_slot_designation,
1250 type,
1251 bandwidth,
1252 usage,
1253 length,
1254 0,
1255 1,
1256 0,
1257 dev->bus->secondary,
1258 dev->path.pci.devfn);
1259 }
1260
1261 int get_smbios_data(struct device *dev, int *handle, unsigned long *current)
1262 {
1263 int len = 0;
1264
1265 len += smbios_generate_type9_from_devtree(dev, handle, current);
1266 len += smbios_generate_type41_from_devtree(dev, handle, current);
1267
1268 return len;
1269 }
1270
1271 static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current)
1272 {
1273 struct device *dev;
1274 int len = 0;
1275
1276 for (dev = tree; dev; dev = dev->next) {
1277 if (!dev->enabled)
1278 continue;
1279
1280 if (dev->ops && dev->ops->get_smbios_data) {
1281 printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev_name(dev));
1282 len += dev->ops->get_smbios_data(dev, handle, current);
1283 } else {
1284 len += get_smbios_data(dev, handle, current);
1285 }
1286 }
1287 return len;
1288 }
1289
1290 unsigned long smbios_write_tables(unsigned long current)
1291 {
1292 struct smbios_entry *se;
1293 struct smbios_entry30 *se3;
1294 unsigned long tables;
1295 int len = 0;
1296 int max_struct_size = 0;
1297 int handle = 0;
1298
1299 current = ALIGN_UP(current, 16);
1300 printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current);
1301
1302 se = (struct smbios_entry *)current;
1303 current += sizeof(*se);
1304 current = ALIGN_UP(current, 16);
1305
1306 se3 = (struct smbios_entry30 *)current;
1307 current += sizeof(*se3);
1308 current = ALIGN_UP(current, 16);
1309
1310 tables = current;
1311 update_max(len, max_struct_size, smbios_write_type0(&current, handle++));
1312 update_max(len, max_struct_size, smbios_write_type1(&current, handle++));
1313
1314 /* The chassis handle is the next one */
1315 update_max(len, max_struct_size, smbios_write_type2(&current, handle, handle + 1));
1316 handle++;
1317 update_max(len, max_struct_size, smbios_write_type3(&current, handle++));
1318
1319 struct smbios_type4 *type4 = (struct smbios_type4 *)current;
1320 update_max(len, max_struct_size, smbios_write_type4(&current, handle++));
1321 len += smbios_write_type7_cache_parameters(&current, &handle, &max_struct_size, type4);
1322 update_max(len, max_struct_size, smbios_write_type11(&current, &handle));
1323 if (CONFIG(ELOG))
1324 update_max(len, max_struct_size,
1325 elog_smbios_write_type15(&current, handle++));
1326
1327 const int type16 = handle;
1328 update_max(len, max_struct_size, smbios_write_type16(&current, &handle));
1329 const int type17 = handle;
1330 update_max(len, max_struct_size, smbios_write_type17(&current, &handle, type16));
1331 const int type19 = handle;
1332 update_max(len, max_struct_size, smbios_write_type19(&current, &handle, type16));
1333 update_max(len, max_struct_size,
1334 smbios_write_type20(&current, &handle, type17, type19));
1335 update_max(len, max_struct_size, smbios_write_type32(&current, handle++));
1336
1337 update_max(len, max_struct_size, smbios_walk_device_tree(all_devices,
1338 &handle, &current));
1339
1340 update_max(len, max_struct_size, smbios_write_type127(&current, handle++));
1341
1342 /* Install SMBIOS 2.1 entry point */
1343 memset(se, 0, sizeof(*se));
1344 memcpy(se->anchor, "_SM_", 4);
1345 se->length = sizeof(*se);
1346 se->major_version = 3;
1347 se->minor_version = 0;
1348 se->max_struct_size = max_struct_size;
1349 se->struct_count = handle;
1350 memcpy(se->intermediate_anchor_string, "_DMI_", 5);
1351
1352 se->struct_table_address = (u32)tables;
1353 se->struct_table_length = len;
1354
1355 se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10, sizeof(*se) - 0x10);
1356 se->checksum = smbios_checksum((u8 *)se, sizeof(*se));
1357
1358 /* Install SMBIOS 3.0 entry point */
1359 memset(se3, 0, sizeof(*se3));
1360 memcpy(se3->anchor, "_SM3_", 5);
1361 se3->length = sizeof(*se3);
1362 se3->major_version = 3;
1363 se3->minor_version = 0;
1364
1365 se3->struct_table_address = (u64)tables;
1366 se3->struct_table_length = len;
1367
1368 se3->checksum = smbios_checksum((u8 *)se3, sizeof(*se3));
1369
1370 return current;
1371 }
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