src/soc/intel/common/block/smm/smm.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <cpu/x86/smm.h>
   5 #include <cpu/intel/smm_reloc.h>
   6 #include <device/mmio.h>
   7 #include <intelblocks/oc_wdt.h>
   8 #include <intelblocks/pmclib.h>
   9 #include <intelblocks/systemagent.h>
  10 #include <soc/pm.h>
  11 #include <soc/pmc.h>
  12
  13 void smm_southbridge_clear_state(void)
  14 {
  15         printk(BIOS_DEBUG, "Clearing SMI status registers\n");
  16
  17         if (pmc_get_smi_en() & APMC_EN) {
  18                 printk(BIOS_INFO, "SMI# handler already enabled?\n");
  19                 return;
  20         }
  21
  22         /* Dump and clear status registers */
  23         pmc_clear_smi_status();
  24         pmc_clear_pm1_status();
  25         pmc_clear_tco_status();
  26         pmc_clear_all_gpe_status();
  27 }
  28
  29 static void configure_periodic_smi_interval(void)
  30 {
  31         uint32_t gen_pmcon;
  32         uint32_t gen_pmcon_reg;
  33
  34         if (CONFIG(PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B))
  35                 gen_pmcon_reg = GEN_PMCON_B;
  36         else
  37                 gen_pmcon_reg = GEN_PMCON_A;
  38
  39         /*
  40          * Periodic SMIs have +/- 1 second error, to be safe add few seconds
  41          * more. Also we do not allow timeouts lower than 70s by Kconfig
  42          * definition, so we need to handle one case.
  43          */
  44         gen_pmcon = read32p(soc_read_pmc_base() + gen_pmcon_reg);
  45         gen_pmcon &= ~PER_SMI_SEL_MASK;
  46         gen_pmcon |= SMI_RATE_64S;
  47         write32p(soc_read_pmc_base() + gen_pmcon_reg, gen_pmcon);
  48
  49         /*
  50          * We don't know when SMI timer is started or even if this is
  51          * architecturally defined, but in worst case we may get SMI 64
  52          * seconds (+ any error) from now, which may be more than OC watchdog
  53          * timeout since it was last kicked, so we should kick it here, just
  54          * in case.
  55          */
  56         oc_wdt_reload();
  57 }
  58
  59 static void smm_southbridge_enable(uint16_t pm1_events)
  60 {
  61         uint32_t smi_params = ENABLE_SMI_PARAMS;
  62
  63         printk(BIOS_DEBUG, "Enabling SMIs.\n");
  64         /* Configure events */
  65         pmc_enable_pm1(pm1_events);
  66         pmc_disable_std_gpe(PME_B0_EN);
  67
  68         /*
  69          * GPEs need to be disabled before enabling SMI. Otherwise, it could
  70          * lead to SMIs being triggered in coreboot preventing the progress of
  71          * normal boot-up. This is done as late as possible so that
  72          * pmc_fill_power_state can read the correct state of GPE0_EN* registers
  73          * and not lose information about the wake source.
  74          */
  75         pmc_disable_all_gpe();
  76
  77         /*
  78          * Enable SMI generation:
  79          *  - on APMC writes (io 0xb2)
  80          *  - on writes to SLP_EN (sleep states)
  81          *  - on writes to GBL_RLS (bios commands)
  82          *  - on eSPI events, unless disabled (does nothing on LPC systems)
  83          *  - on TCO events (TIMEOUT, case intrusion, ...), if enabled
  84          *  - periodically, if watchdog feeding through SMI is enabled
  85          * No SMIs:
  86          *  - on microcontroller writes (io 0x62/0x66)
  87          */
  88         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE))
  89                 smi_params &= ~ESPI_SMI_EN;
  90
  91         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE))
  92                 smi_params |= TCO_SMI_EN;
  93
  94         if (CONFIG(SOC_INTEL_COMMON_OC_WDT_RELOAD_IN_PERIODIC_SMI)) {
  95                 smi_params |= PERIODIC_EN;
  96                 configure_periodic_smi_interval();
  97         }
  98
  99         /* Enable SMI generation: */
 100         pmc_enable_smi(smi_params);
 101 }
 102
 103 void global_smi_enable(void)
 104 {
 105         smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 106 }
 107
 108 void global_smi_enable_no_pwrbtn(void)
 109 {
 110         smm_southbridge_enable(GBL_EN);
 111 }