src/southbridge/intel/bd82x6x/acpi/pch.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* Intel Cougar Point PCH support */
   4 #include <southbridge/intel/bd82x6x/pch.h>
   5
   6 Scope(\)
   7 {
   8         // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
   9         OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
  10         Field(PMIO, ByteAcc, NoLock, Preserve)
  11         {
  12                 Offset(0x20),   // GPE0_STS
  13                 , 16,
  14                 GS00, 1,        // GPIO00 SCI/Wake Status
  15                 GS01, 1,        // GPIO01 SCI/Wake Status
  16                 GS02, 1,        // GPIO02 SCI/Wake Status
  17                 GS03, 1,        // GPIO03 SCI/Wake Status
  18                 GS04, 1,        // GPIO04 SCI/Wake Status
  19                 GS05, 1,        // GPIO05 SCI/Wake Status
  20                 GS06, 1,        // GPIO06 SCI/Wake Status
  21                 GS07, 1,        // GPIO07 SCI/Wake Status
  22                 GS08, 1,        // GPIO08 SCI/Wake Status
  23                 GS09, 1,        // GPIO09 SCI/Wake Status
  24                 GS10, 1,        // GPIO10 SCI/Wake Status
  25                 GS11, 1,        // GPIO11 SCI/Wake Status
  26                 GS12, 1,        // GPIO12 SCI/Wake Status
  27                 GS13, 1,        // GPIO13 SCI/Wake Status
  28                 GS14, 1,        // GPIO14 SCI/Wake Status
  29                 GS15, 1,        // GPIO15 SCI/Wake Status
  30                 Offset(0x28),   // GPE0_EN
  31                 , 16,
  32                 GE00, 1,        // GPIO00 SCI/Wake Enable
  33                 GE01, 1,        // GPIO01 SCI/Wake Enable
  34                 GE02, 1,        // GPIO02 SCI/Wake Enable
  35                 GE03, 1,        // GPIO03 SCI/Wake Enable
  36                 GE04, 1,        // GPIO04 SCI/Wake Enable
  37                 GE05, 1,        // GPIO05 SCI/Wake Enable
  38                 GE06, 1,        // GPIO06 SCI/Wake Enable
  39                 GE07, 1,        // GPIO07 SCI/Wake Enable
  40                 GE08, 1,        // GPIO08 SCI/Wake Enable
  41                 GE09, 1,        // GPIO09 SCI/Wake Enable
  42                 GE10, 1,        // GPIO10 SCI/Wake Enable
  43                 GE11, 1,        // GPIO11 SCI/Wake Enable
  44                 GE12, 1,        // GPIO12 SCI/Wake Enable
  45                 GE13, 1,        // GPIO13 SCI/Wake Enable
  46                 GE14, 1,        // GPIO14 SCI/Wake Enable
  47                 GE15, 1,        // GPIO15 SCI/Wake Enable
  48                 Offset(0x42),   // General Purpose Control
  49                 , 1,            // skip 1 bit
  50                 GPEC, 1,        // SWGPE_CTRL
  51         }
  52
  53         // GPIO IO mapped registers (0x1f.0 reg 0x48.l)
  54         OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
  55         Field(GPIO, ByteAcc, NoLock, Preserve)
  56         {
  57                 GU00, 8,        // GPIO Use Select
  58                 GU01, 8,
  59                 GU02, 8,
  60                 GU03, 8,
  61                 Offset(0x04),   // GPIO IO Select
  62                 GIO0, 8,
  63                 GIO1, 8,
  64                 GIO2, 8,
  65                 GIO3, 8,
  66                 Offset(0x0c),   // GPIO Level
  67                 GP00, 1,
  68                 GP01, 1,
  69                 GP02, 1,
  70                 GP03, 1,
  71                 GP04, 1,
  72                 GP05, 1,
  73                 GP06, 1,
  74                 GP07, 1,
  75                 GP08, 1,
  76                 GP09, 1,
  77                 GP10, 1,
  78                 GP11, 1,
  79                 GP12, 1,
  80                 GP13, 1,
  81                 GP14, 1,
  82                 GP15, 1,
  83                 GP16, 1,
  84                 GP17, 1,
  85                 GP18, 1,
  86                 GP19, 1,
  87                 GP20, 1,
  88                 GP21, 1,
  89                 GP22, 1,
  90                 GP23, 1,
  91                 GP24, 1,
  92                 GP25, 1,
  93                 GP26, 1,
  94                 GP27, 1,
  95                 GP28, 1,
  96                 GP29, 1,
  97                 GP30, 1,
  98                 GP31, 1,
  99                 Offset(0x18),   // GPIO Blink
 100                 GB00, 8,
 101                 GB01, 8,
 102                 GB02, 8,
 103                 GB03, 8,
 104                 Offset(0x2c),   // GPIO Invert
 105                 GIV0, 8,
 106                 GIV1, 8,
 107                 GIV2, 8,
 108                 GIV3, 8,
 109                 Offset(0x30),   // GPIO Use Select 2
 110                 GU04, 8,
 111                 GU05, 8,
 112                 GU06, 8,
 113                 GU07, 8,
 114                 Offset(0x34),   // GPIO IO Select 2
 115                 GIO4, 8,
 116                 GIO5, 8,
 117                 GIO6, 8,
 118                 GIO7, 8,
 119                 Offset(0x38),   // GPIO Level 2
 120                 GP32, 1,
 121                 GP33, 1,
 122                 GP34, 1,
 123                 GP35, 1,
 124                 GP36, 1,
 125                 GP37, 1,
 126                 GP38, 1,
 127                 GP39, 1,
 128                 GP40, 1,
 129                 GP41, 1,
 130                 GP42, 1,
 131                 GP43, 1,
 132                 GP44, 1,
 133                 GP45, 1,
 134                 GP46, 1,
 135                 GP47, 1,
 136                 GP48, 1,
 137                 GP49, 1,
 138                 GP50, 1,
 139                 GP51, 1,
 140                 GP52, 1,
 141                 GP53, 1,
 142                 GP54, 1,
 143                 GP55, 1,
 144                 GP56, 1,
 145                 GP57, 1,
 146                 GP58, 1,
 147                 GP59, 1,
 148                 GP60, 1,
 149                 GP61, 1,
 150                 GP62, 1,
 151                 GP63, 1,
 152                 Offset(0x40),   // GPIO Use Select 3
 153                 GU08, 8,
 154                 GU09, 4,
 155                 Offset(0x44),   // GPIO IO Select 3
 156                 GIO8, 8,
 157                 GIO9, 4,
 158                 Offset(0x48),   // GPIO Level 3
 159                 GP64, 1,
 160                 GP65, 1,
 161                 GP66, 1,
 162                 GP67, 1,
 163                 GP68, 1,
 164                 GP69, 1,
 165                 GP70, 1,
 166                 GP71, 1,
 167                 GP72, 1,
 168                 GP73, 1,
 169                 GP74, 1,
 170                 GP75, 1,
 171         }
 172
 173
 174         // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
 175         OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
 176         Field(RCRB, DWordAcc, Lock, Preserve)
 177         {
 178                 Offset(0x0000), // Backbone
 179                 Offset(0x1000), // Chipset
 180                 Offset(0x3000), // Legacy Configuration Registers
 181                 Offset(0x3404), // High Performance Timer Configuration
 182                 HPAS, 2,        // Address Select
 183                 , 5,
 184                 HPTE, 1,        // Address Enable
 185                 Offset(0x3418), // FD (Function Disable)
 186                 , 1,            // Reserved
 187                 PCID, 1,        // PCI bridge disable
 188                 SA1D, 1,        // SATA1 disable
 189                 SMBD, 1,        // SMBUS disable
 190                 HDAD, 1,        // Azalia disable
 191                 , 8,            // Reserved
 192                 EH2D, 1,        // EHCI #2 disable
 193                 LPBD, 1,        // LPC bridge disable
 194                 EH1D, 1,        // EHCI #1 disable
 195                 RP1D, 1,        // Root Port 1 disable
 196                 RP2D, 1,        // Root Port 2 disable
 197                 RP3D, 1,        // Root Port 3 disable
 198                 RP4D, 1,        // Root Port 4 disable
 199                 RP5D, 1,        // Root Port 5 disable
 200                 RP6D, 1,        // Root Port 6 disable
 201                 RP7D, 1,        // Root Port 7 disable
 202                 RP8D, 1,        // Root Port 8 disable
 203                 TTRD, 1,        // Thermal sensor registers disable
 204                 SA2D, 1,        // SATA2 disable
 205                 Offset(0x3428), // FD2 (Function Disable 2)
 206                 BDFD, 1,        // Display BDF
 207                 ME1D, 1,        // ME Interface 1 disable
 208                 ME2D, 1,        // ME Interface 2 disable
 209                 IDRD, 1,        // IDE redirect disable
 210                 KTCT, 1,        // Keyboard Text redirect disable
 211         }
 212 }
 213
 214 // High Definition Audio (Azalia) 0:1b.0
 215 #include "audio.asl"
 216
 217 // PCI Express Ports 0:1c.x
 218 #include <southbridge/intel/common/acpi/pcie.asl>
 219
 220 // USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0
 221 #include "usb.asl"
 222
 223 // LPC Bridge 0:1f.0
 224 #include "lpc.asl"
 225
 226 // SATA 0:1f.2, 0:1f.5
 227 #include "sata.asl"
 228
 229 // SMBus 0:1f.3
 230 #include <southbridge/intel/common/acpi/smbus.asl>
 231
 232 Method (_OSC, 4)
 233 {
 234         /*
 235          * Arg0 - A Buffer containing a UUID
 236          * Arg1 - An Integer containing a Revision ID of the buffer format
 237          * Arg2 - An Integer containing a count of entries in Arg3
 238          * Arg3 - A Buffer containing a list of DWORD capabilities
 239          */
 240         /* Check for XHCI */
 241         If (Arg0 == ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))
 242         {
 243                 Return (^XHC.POSC(Arg2, Arg3))
 244         }
 245
 246         /* Check for PCIe */
 247         If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
 248         {
 249                 /* Let OS control everything */
 250                 Return (Arg3)
 251         }
 252
 253         /* Else Return Unrecognized UUID */
 254         CreateDWordField (Arg3, 0, CDW1)
 255         CDW1 |= 4
 256         Return (Arg3)
 257
 258 }