1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include <device/pci_def.h>
6 #include <southbridge/intel/common/rcba.h>
7 #include <southbridge/intel/common/pmbase.h>
11 void early_usb_init(const struct southbridge_usb_port
*portmap
)
14 const u32 rcba_dump
[8] = {
15 /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
16 /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
18 const u32 currents
[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51,
19 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357,
23 /* Unlock registers. */
24 write_pmbase16(UPRWC
, read_pmbase16(UPRWC
) | UPRWC_WR_EN
);
26 for (i
= 0; i
< 14; i
++)
27 RCBA32(USBIR0
+ 4 * i
) = currents
[portmap
[i
].current
];
28 for (i
= 0; i
< 10; i
++)
29 RCBA32(0x3538 + 4 * i
) = 0;
31 for (i
= 0; i
< 8; i
++)
32 RCBA32(0x3560 + 4 * i
) = rcba_dump
[i
];
33 for (i
= 0; i
< 8; i
++)
34 RCBA32(0x3580 + 4 * i
) = 0;
36 for (i
= 0; i
< 14; i
++)
37 if (!portmap
[i
].enabled
)
39 RCBA32(USBPDO
) = reg32
;
41 for (i
= 0; i
< 8; i
++)
42 if (portmap
[i
].enabled
&& portmap
[i
].oc_pin
>= 0)
43 reg32
|= (1 << (i
+ 8 * portmap
[i
].oc_pin
));
44 RCBA32(USBOCM1
) = reg32
;
46 for (i
= 8; i
< 14; i
++)
47 if (portmap
[i
].enabled
&& portmap
[i
].oc_pin
>= 4)
48 reg32
|= (1 << (i
- 8 + 8 * (portmap
[i
].oc_pin
- 4)));
49 RCBA32(USBOCM2
) = reg32
;
50 for (i
= 0; i
< 22; i
++)
51 RCBA32(0x35a8 + 4 * i
) = 0;
53 pci_write_config32(PCH_XHCI_DEV
, 0xe4, 0x00000000);
55 /* Relock registers. */
56 write_pmbase16(UPRWC
, 0);