src/southbridge/intel/bd82x6x/pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <delay.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <device/pci_ops.h>
   8 #include <string.h>
   9
  10 #include "chip.h"
  11 #include "pch.h"
  12
  13 int pch_silicon_revision(void)
  14 {
  15         static int pch_revision_id = -1;
  16
  17 #ifdef __SIMPLE_DEVICE__
  18         pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
  19 #else
  20         struct device *dev = pcidev_on_root(0x1f, 0);
  21 #endif
  22
  23         if (pch_revision_id < 0)
  24                 pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
  25         return pch_revision_id;
  26 }
  27
  28 int pch_silicon_type(void)
  29 {
  30         static int pch_type = -1;
  31
  32 #ifdef __SIMPLE_DEVICE__
  33         pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
  34 #else
  35         struct device *dev = pcidev_on_root(0x1f, 0);
  36 #endif
  37
  38         if (pch_type < 0)
  39                 pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
  40         return pch_type;
  41 }
  42
  43 static int pch_silicon_supported(int type, int rev)
  44 {
  45         int cur_type = pch_silicon_type();
  46         int cur_rev = pch_silicon_revision();
  47
  48         switch (type) {
  49         case PCH_TYPE_CPT:
  50                 /* CougarPoint minimum revision */
  51                 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
  52                         return 1;
  53                 /* PantherPoint any revision */
  54                 if (cur_type == PCH_TYPE_PPT)
  55                         return 1;
  56                 break;
  57
  58         case PCH_TYPE_PPT:
  59                 /* PantherPoint minimum revision */
  60                 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
  61                         return 1;
  62                 break;
  63         }
  64
  65         return 0;
  66 }
  67
  68 #define IOBP_RETRY 1000
  69 static inline int iobp_poll(void)
  70 {
  71         unsigned int try = IOBP_RETRY;
  72         u32 data;
  73
  74         while (try--) {
  75                 data = RCBA32(IOBPS);
  76                 if ((data & 1) == 0)
  77                         return 1;
  78                 udelay(10);
  79         }
  80
  81         printk(BIOS_ERR, "IOBP timeout\n");
  82         return 0;
  83 }
  84
  85 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
  86 {
  87         u32 data;
  88
  89         /* Set the address */
  90         RCBA32(IOBPIRI) = address;
  91
  92         /* READ OPCODE */
  93         if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
  94                 RCBA32(IOBPS) = IOBPS_RW_BX;
  95         else
  96                 RCBA32(IOBPS) = IOBPS_READ_AX;
  97         if (!iobp_poll())
  98                 return;
  99
 100         /* Read IOBP data */
 101         data = RCBA32(IOBPD);
 102         if (!iobp_poll())
 103                 return;
 104
 105         /* Check for successful transaction */
 106         if ((RCBA32(IOBPS) & 0x6) != 0) {
 107                 printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
 108                 return;
 109         }
 110
 111         /* Update the data */
 112         data &= andvalue;
 113         data |= orvalue;
 114
 115         /* WRITE OPCODE */
 116         if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
 117                 RCBA32(IOBPS) = IOBPS_RW_BX;
 118         else
 119                 RCBA32(IOBPS) = IOBPS_WRITE_AX;
 120         if (!iobp_poll())
 121                 return;
 122
 123         /* Write IOBP data */
 124         RCBA32(IOBPD) = data;
 125         if (!iobp_poll())
 126                 return;
 127 }
 128
 129 #ifndef __SIMPLE_DEVICE__
 130 /* Set bit in function disable register to hide this device */
 131 static void pch_hide_devfn(unsigned int devfn)
 132 {
 133         switch (devfn) {
 134         case PCI_DEVFN(20, 0): /* xHCI */
 135                 if (pch_silicon_type() == PCH_TYPE_PPT) {
 136                         /* on CPT this bit is reserved */
 137                         RCBA32_OR(FD, PCH_DISABLE_XHCI);
 138                 }
 139                 break;
 140         case PCI_DEVFN(22, 0): /* MEI #1 */
 141                 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
 142                 break;
 143         case PCI_DEVFN(22, 1): /* MEI #2 */
 144                 RCBA32_OR(FD2, PCH_DISABLE_MEI2);
 145                 break;
 146         case PCI_DEVFN(22, 2): /* IDE-R */
 147                 RCBA32_OR(FD2, PCH_DISABLE_IDER);
 148                 break;
 149         case PCI_DEVFN(22, 3): /* KT */
 150                 RCBA32_OR(FD2, PCH_DISABLE_KT);
 151                 break;
 152         case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
 153                 /* BUC is already handled in `early_pch.c`. */
 154                 break;
 155         case PCI_DEVFN(26, 0): /* EHCI #2 */
 156                 RCBA32_OR(FD, PCH_DISABLE_EHCI2);
 157                 break;
 158         case PCI_DEVFN(27, 0): /* HD Audio Controller */
 159                 RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
 160                 break;
 161         case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
 162         case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
 163         case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
 164         case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
 165         case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
 166         case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
 167         case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
 168         case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
 169                 RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn)));
 170                 break;
 171         case PCI_DEVFN(29, 0): /* EHCI #1 */
 172                 RCBA32_OR(FD, PCH_DISABLE_EHCI1);
 173                 break;
 174         case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */
 175                 RCBA32_OR(FD, PCH_DISABLE_P2P);
 176                 break;
 177         case PCI_DEVFN(31, 0): /* LPC */
 178                 RCBA32_OR(FD, PCH_DISABLE_LPC);
 179                 break;
 180         case PCI_DEVFN(31, 2): /* SATA #1 */
 181                 RCBA32_OR(FD, PCH_DISABLE_SATA1);
 182                 break;
 183         case PCI_DEVFN(31, 3): /* SMBUS */
 184                 RCBA32_OR(FD, PCH_DISABLE_SMBUS);
 185                 break;
 186         case PCI_DEVFN(31, 5): /* SATA #22 */
 187                 RCBA32_OR(FD, PCH_DISABLE_SATA2);
 188                 break;
 189         case PCI_DEVFN(31, 6): /* Thermal Subsystem */
 190                 RCBA32_OR(FD, PCH_DISABLE_THERMAL);
 191                 break;
 192         }
 193 }
 194
 195 /* Check if any port in set X to X+3 is enabled */
 196 static int pch_pcie_check_set_enabled(struct device *dev)
 197 {
 198         struct device *port;
 199         int port_func;
 200         int dev_func = PCI_FUNC(dev->path.pci.devfn);
 201
 202         printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev));
 203
 204         /* Go through static device tree list of devices
 205          * because enumeration is still in progress */
 206         for (port = all_devices; port; port = port->next) {
 207                 /* Only care about PCIe root ports */
 208                 if (PCI_SLOT(port->path.pci.devfn) !=
 209                     PCI_SLOT(dev->path.pci.devfn))
 210                         continue;
 211
 212                 /* Check if port is in range and enabled */
 213                 port_func = PCI_FUNC(port->path.pci.devfn);
 214                 if (port_func >= dev_func &&
 215                     port_func < (dev_func + 4) &&
 216                     port->enabled)
 217                         return 1;
 218         }
 219
 220         /* None of the ports in this set are enabled */
 221         return 0;
 222 }
 223
 224 /* RPFN is a write-once register so keep a copy until it is written */
 225 static u32 new_rpfn;
 226
 227 /* Swap function numbers assigned to two PCIe Root Ports */
 228 static void pch_pcie_function_swap(u8 old_fn, u8 new_fn)
 229 {
 230         u32 old_rpfn = new_rpfn;
 231
 232         printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n",
 233                old_fn, new_fn);
 234
 235         new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn));
 236
 237         /* Old function set to new function and disabled */
 238         new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn));
 239         new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn));
 240 }
 241
 242 /* Update devicetree with new Root Port function number assignment */
 243 static void pch_pcie_devicetree_update(
 244                 struct southbridge_intel_bd82x6x_config *config)
 245 {
 246         struct device *dev;
 247
 248         /*
 249          * hotplug map should also be updated along with their
 250          * corresponding port
 251          */
 252         u8 new_hotplug_map[sizeof(config->pcie_hotplug_map)];
 253
 254         /*
 255          * Slots that didn't move need the hotplug setting copied too,
 256          * so "new_hotplug_map" is initialized with the values of the old map.
 257          */
 258         memcpy(new_hotplug_map, config->pcie_hotplug_map,
 259                sizeof(new_hotplug_map));
 260
 261         /* Update the function numbers in the static devicetree */
 262         for (dev = all_devices; dev; dev = dev->next) {
 263                 u8 new_devfn;
 264
 265                 /* Only care about PCH PCIe root ports */
 266                 if (PCI_SLOT(dev->path.pci.devfn) !=
 267                     PCH_PCIE_DEV_SLOT)
 268                         continue;
 269
 270                 /* Determine the new devfn for this port */
 271                 new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT,
 272                               RPFN_FNGET(new_rpfn,
 273                                  PCI_FUNC(dev->path.pci.devfn)));
 274
 275                 if (dev->path.pci.devfn != new_devfn) {
 276                         printk(BIOS_DEBUG,
 277                                "PCH: PCIe map %02x.%1x -> %02x.%1x\n",
 278                                PCI_SLOT(dev->path.pci.devfn),
 279                                PCI_FUNC(dev->path.pci.devfn),
 280                                PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
 281
 282                         /*
 283                          * Copy the flag to its new position along with
 284                          * the corresponding port
 285                          */
 286                         new_hotplug_map[PCI_FUNC(new_devfn)] =
 287                                 config->pcie_hotplug_map
 288                                 [PCI_FUNC(dev->path.pci.devfn)];
 289
 290                         dev->path.pci.devfn = new_devfn;
 291                 }
 292         }
 293
 294         /* Copy the updated map back to its place */
 295         memcpy(config->pcie_hotplug_map, new_hotplug_map,
 296                sizeof(new_hotplug_map));
 297 }
 298
 299 /* Special handling for PCIe Root Port devices */
 300 static void pch_pcie_enable(struct device *dev)
 301 {
 302         struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 303
 304         if (!config)
 305                 return;
 306
 307         /*
 308          * Save a copy of the Root Port Function Number map when
 309          * starting to walk the list of PCIe Root Ports so it can
 310          * be updated locally and written out when the last port
 311          * has been processed.
 312          */
 313         if (PCI_FUNC(dev->path.pci.devfn) == 0) {
 314                 new_rpfn = RCBA32(RPFN);
 315
 316                 /*
 317                  * Enable Root Port coalescing if the first port is disabled
 318                  * or the other devices will not be enumerated by the OS.
 319                  */
 320                 if (!dev->enabled)
 321                         config->pcie_port_coalesce = true;
 322
 323                 if (config->pcie_port_coalesce)
 324                         printk(BIOS_INFO,
 325                                "PCH: PCIe Root Port coalescing is enabled\n");
 326         }
 327
 328         if (!dev->enabled) {
 329                 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
 330
 331                 /*
 332                  * PCIE Power Savings for PantherPoint and CougarPoint/B1+
 333                  *
 334                  * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1
 335                  * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1
 336                  *
 337                  * This check is done here instead of PCIe driver
 338                  * because the PCIe driver enable() handler is not
 339                  * called unless the device is enabled.
 340                  */
 341                 if ((PCI_FUNC(dev->path.pci.devfn) == 0 ||
 342                      PCI_FUNC(dev->path.pci.devfn) == 4)) {
 343                         /* Handle workaround for PPT and CPT/B1+ */
 344                         if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) &&
 345                             !pch_pcie_check_set_enabled(dev)) {
 346                                 pci_or_config8(dev, 0xe2, 1);
 347                         }
 348
 349                         /*
 350                          * Enable Clock Gating for shared PCIe resources
 351                          * before disabling this particular port.
 352                          */
 353                         pci_write_config8(dev, 0xe1, 0x3c);
 354                 }
 355
 356                 /* Ensure memory, io, and bus master are all disabled */
 357                 pci_and_config16(dev, PCI_COMMAND,
 358                                  ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 359
 360                 /* Do not claim downstream transactions for PCIe ports */
 361                 new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
 362
 363                 /* Hide this device if possible */
 364                 pch_hide_devfn(dev->path.pci.devfn);
 365         } else {
 366                 int fn;
 367
 368                 /*
 369                  * Check if there is a lower disabled port to swap with this
 370                  * port in order to maintain linear order starting at zero.
 371                  */
 372                 if (config->pcie_port_coalesce) {
 373                         for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) {
 374                                 if (!(new_rpfn & RPFN_HIDE(fn)))
 375                                         continue;
 376
 377                                 /* Swap places with this function */
 378                                 pch_pcie_function_swap(
 379                                         PCI_FUNC(dev->path.pci.devfn), fn);
 380                                 break;
 381                         }
 382                 }
 383
 384                 /* Enable SERR */
 385                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 386         }
 387
 388         /*
 389          * When processing the last PCIe root port we can now
 390          * update the Root Port Function Number and Hide register.
 391          */
 392         if (PCI_FUNC(dev->path.pci.devfn) == 7) {
 393                 printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
 394                        RCBA32(RPFN), new_rpfn);
 395                 RCBA32(RPFN) = new_rpfn;
 396
 397                 /* Update static devictree with new function numbers */
 398                 if (config->pcie_port_coalesce)
 399                         pch_pcie_devicetree_update(config);
 400         }
 401 }
 402
 403 void pch_enable(struct device *dev)
 404 {
 405         /* PCH PCIe Root Ports get special handling */
 406         if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT)
 407                 return pch_pcie_enable(dev);
 408
 409         if (!dev->enabled) {
 410                 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
 411
 412                 /* Ensure memory, io, and bus master are all disabled */
 413                 pci_and_config16(dev, PCI_COMMAND,
 414                                  ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 415
 416                 /* Hide this device if possible */
 417                 pch_hide_devfn(dev->path.pci.devfn);
 418         } else {
 419                 /* Enable SERR */
 420                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 421         }
 422 }
 423
 424 struct chip_operations southbridge_intel_bd82x6x_ops = {
 425         CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge")
 426         .enable_dev = pch_enable,
 427 };
 428 #endif