1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <device/pci_ops.h>
8 #include <device/pci_ids.h>
9 #include <pc80/isa-dma.h>
10 #include <pc80/mc146818rtc.h>
11 #include <arch/ioapic.h>
12 #if CONFIG(HAVE_ACPI_TABLES)
13 #include <acpi/acpi.h>
14 #include <acpi/acpigen.h>
19 static void isa_init(struct device
*dev
)
22 struct southbridge_intel_i82371eb_config
*sb
= dev
->chip_info
;
24 /* Initialize the real time clock (RTC). */
28 * Enable special cycles, needed for soft poweroff.
30 pci_or_config16(dev
, PCI_COMMAND
, PCI_COMMAND_SPECIAL
);
33 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
34 * bus, which is a subset of ISA. We select the full ISA bus here.
36 reg32
= pci_read_config32(dev
, GENCFG
);
37 reg32
|= ISA
; /* Select ISA, not EIO. */
39 /* Some boards use GPO22/23. Select it if configured. */
40 reg32
= ONOFF(sb
->gpo22_enable
, reg32
, GPO2223
);
41 pci_write_config32(dev
, GENCFG
, reg32
);
43 /* Initialize ISA DMA. */
47 * Unlike most other southbridges the 82371EB doesn't have a built-in
48 * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
49 * have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
51 * Thus, we can/must only enable the IOAPIC if it actually exists,
52 * i.e. the respective mainboard does "select IOAPIC".
59 reg16
= pci_read_config16(dev
, XBCS
);
60 reg16
|= (1 << 8); /* APIC Chip Select */
61 pci_write_config16(dev
, XBCS
, reg16
);
63 /* Set and verify the IOAPIC ID. */
64 setup_ioapic(VIO_APIC_VADDR
, ioapic_id
);
65 if (ioapic_id
!= get_ioapic_id(VIO_APIC_VADDR
))
66 die("IOAPIC error!\n");
70 static void sb_read_resources(struct device
*dev
)
74 pci_dev_read_resources(dev
);
76 res
= new_resource(dev
, 1);
79 res
->limit
= 0xffffUL
;
80 res
->flags
= IORESOURCE_IO
| IORESOURCE_ASSIGNED
| IORESOURCE_FIXED
;
82 res
= new_resource(dev
, 2);
83 res
->base
= 0xff800000UL
;
84 res
->size
= 0x00800000UL
; /* 8 MB for flash */
85 res
->flags
= IORESOURCE_MEM
| IORESOURCE_ASSIGNED
| IORESOURCE_FIXED
|
88 res
= new_resource(dev
, 3); /* IOAPIC */
89 res
->base
= IO_APIC_ADDR
;
90 res
->size
= 0x00001000;
91 res
->flags
= IORESOURCE_MEM
| IORESOURCE_ASSIGNED
| IORESOURCE_FIXED
|
95 static const struct device_operations isa_ops
= {
96 .read_resources
= sb_read_resources
,
97 .set_resources
= pci_dev_set_resources
,
98 .enable_resources
= pci_dev_enable_resources
,
99 #if CONFIG(HAVE_ACPI_TABLES)
100 .write_acpi_tables
= acpi_write_hpet
,
101 .acpi_fill_ssdt
= generate_cpu_entries
,
104 .scan_bus
= scan_static_bus
,
105 .ops_pci
= 0, /* No subsystem IDs on 82371EB! */
108 static const struct pci_driver isa_driver __pci_driver
= {
110 .vendor
= PCI_VID_INTEL
,
111 .device
= PCI_DID_INTEL_82371AB_ISA
,
114 static const struct pci_driver isa_SB_driver __pci_driver
= {
116 .vendor
= PCI_VID_INTEL
,
117 .device
= PCI_DID_INTEL_82371SB_ISA
,