src/southbridge/intel/i82371eb/smbus.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <arch/io.h>
   4 #include <device/pci_ops.h>
   5 #include <console/console.h>
   6 #include <stdint.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <device/smbus.h>
  11 #include "chip.h"
  12 #include "i82371eb.h"
  13
  14 static void pwrmgt_enable(struct device *dev)
  15 {
  16         struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
  17         u32 reg, gpo = sb->gpo;
  18
  19         /* Sets the base address of power management ports. */
  20         pci_write_config16(dev, PMBA, DEFAULT_PMBASE | 1);
  21
  22         /* Set Power Management IO Space Enable bit */
  23         u8 val = pci_read_config8(dev, PMREGMISC);
  24         pci_write_config8(dev, PMREGMISC, val | 1);
  25
  26         /* set global control:
  27          * bit25 (lid_pol): 1=invert lid polarity
  28          * bit24 (sm_freeze): 1=freeze idle and standby timers
  29          * bit16 (end of smi): 0=disable smi assertion (cleared by hw)
  30          * bits8-15,26: global standby timer initial count 127 * 4minutes
  31          * bit2  (thrm_pol): 1=active low THRM#
  32          * bit0  (smi_en): 1=disable smi generation upon smi event
  33          */
  34         reg = (sb->lid_polarity<<25)|
  35               (1<<24)|
  36               (0xff<<8)|
  37               (sb->thrm_polarity<<2);
  38         outl(reg, DEFAULT_PMBASE + GLBCTL);
  39
  40         /* set processor control:
  41          * bit12 (stpclk_en): 1=enable stopping of host clk on lvl3
  42          * bit11 (sleep_en): 1=enable slp# assertion on lvl3
  43          * bit9 (cc_en): 1=enable clk control with lvl2 and lvl3 regs
  44          */
  45         outl(0, DEFAULT_PMBASE + PCNTRL);
  46
  47         /* disable smi event enables */
  48         outw(0, DEFAULT_PMBASE + GLBEN);
  49         outl(0, DEFAULT_PMBASE + DEVCTL);
  50
  51         /* set default gpo value.
  52          * power-on default is 0x7fffbfffh */
  53         if (gpo) {
  54                 /* only 8bit access allowed */
  55                 outb(gpo        & 0xff, DEFAULT_PMBASE + GPO0);
  56                 outb((gpo >>  8) & 0xff, DEFAULT_PMBASE + GPO1);
  57                 outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2);
  58                 outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3);
  59         } else {
  60                 printk(BIOS_SPEW,
  61                        "%s: gpo default missing in devicetree.cb!\n", __func__);
  62         }
  63
  64         /* Clear status events. */
  65         outw(0xffff,     DEFAULT_PMBASE + PMSTS);
  66         outw(0xffff,     DEFAULT_PMBASE + GPSTS);
  67         outw(0xffff,     DEFAULT_PMBASE + GLBSTS);
  68         outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
  69
  70         /* set PMCNTRL default */
  71         outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
  72 }
  73
  74 static void pwrmgt_read_resources(struct device *dev)
  75 {
  76         struct resource *res;
  77
  78         pci_dev_read_resources(dev);
  79
  80         res = new_resource(dev, 1);
  81         res->base = DEFAULT_PMBASE;
  82         res->size = 0x0040;
  83         res->limit = 0xffff;
  84         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
  85                      IORESOURCE_RESERVE;
  86
  87         res = new_resource(dev, 2);
  88         res->base = SMBUS_IO_BASE;
  89         res->size = 0x0010;
  90         res->limit = 0xffff;
  91         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
  92                      IORESOURCE_RESERVE;
  93 }
  94
  95 static const struct smbus_bus_operations lops_smbus_bus = {
  96 };
  97
  98 static const struct device_operations smbus_ops = {
  99         .read_resources         = pwrmgt_read_resources,
 100         .set_resources          = pci_dev_set_resources,
 101         .enable_resources       = pci_dev_enable_resources,
 102         .scan_bus               = scan_smbus,
 103         .enable                 = pwrmgt_enable,
 104         .ops_pci                = 0, /* No subsystem IDs on 82371EB! */
 105         .ops_smbus_bus          = &lops_smbus_bus,
 106 };
 107
 108 /* Note: There's no SMBus on 82371FB/SB/MX and 82437MX. */
 109
 110 /* Intel 82371AB/EB/MB */
 111 static const struct pci_driver smbus_driver __pci_driver = {
 112         .ops    = &smbus_ops,
 113         .vendor = PCI_VID_INTEL,
 114         .device = PCI_DID_INTEL_82371AB_SMB_ACPI,
 115 };