src/southbridge/intel/i82801ix/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
   4 #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
   5
   6 #include <stdint.h>
   7
   8 enum {
   9         THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3,
  10         THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7
  11 };
  12
  13 struct southbridge_intel_i82801ix_config {
  14         /**
  15          * Interrupt Routing configuration
  16          * If bit7 is 1, the interrupt is disabled.
  17          */
  18         uint8_t pirqa_routing;
  19         uint8_t pirqb_routing;
  20         uint8_t pirqc_routing;
  21         uint8_t pirqd_routing;
  22         uint8_t pirqe_routing;
  23         uint8_t pirqf_routing;
  24         uint8_t pirqg_routing;
  25         uint8_t pirqh_routing;
  26
  27         /**
  28          * GPI Routing configuration
  29          *
  30          * Only the lower two bits have a meaning:
  31          * 00: No effect
  32          * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
  33          * 10: SCI (if corresponding GPIO_EN bit is also set)
  34          * 11: reserved
  35          */
  36         uint8_t gpi0_routing;
  37         uint8_t gpi1_routing;
  38         uint8_t gpi2_routing;
  39         uint8_t gpi3_routing;
  40         uint8_t gpi4_routing;
  41         uint8_t gpi5_routing;
  42         uint8_t gpi6_routing;
  43         uint8_t gpi7_routing;
  44         uint8_t gpi8_routing;
  45         uint8_t gpi9_routing;
  46         uint8_t gpi10_routing;
  47         uint8_t gpi11_routing;
  48         uint8_t gpi12_routing;
  49         uint8_t gpi13_routing;
  50         uint8_t gpi14_routing;
  51         uint8_t gpi15_routing;
  52
  53         uint32_t gpe0_en;
  54         uint16_t alt_gp_smi_en;
  55
  56         /* IDE configuration */
  57         uint8_t sata_port_map : 6;
  58         unsigned int sata_clock_request : 1;
  59         unsigned int sata_traffic_monitor : 1;
  60
  61         unsigned int c4onc3_enable:1;
  62         unsigned int c5_enable : 1;
  63         unsigned int c6_enable : 1;
  64
  65         unsigned int throttle_duty : 3;
  66
  67         /* Bit mask to tell whether a PCIe slot is implemented as slot. */
  68         unsigned int pcie_slot_implemented : 6;
  69
  70         /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
  71         struct {
  72                 uint8_t value : 8;
  73                 uint8_t scale : 2;
  74         } pcie_power_limits[6];
  75
  76         uint8_t pcie_hotplug_map[8];
  77
  78         /* Additional LPC IO decode ranges */
  79         uint32_t gen1_dec;
  80         uint32_t gen2_dec;
  81         uint32_t gen3_dec;
  82         uint32_t gen4_dec;
  83 };
  84
  85 #endif                          /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */