src/southbridge/intel/i82801jx/i82801jx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOUTHBRIDGE_INTEL_I82801JX_I82801JX_H
   4 #define SOUTHBRIDGE_INTEL_I82801JX_I82801JX_H
   5
   6 #define DEFAULT_TBAR            ((u8 *)0xfed1b000)
   7
   8 #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */
   9
  10 #define DEFAULT_PMBASE          0x00000500
  11 #define DEFAULT_TCOBASE         (DEFAULT_PMBASE + 0x60)
  12 #define DEFAULT_GPIOBASE        0x00000580
  13
  14 #define APM_CNT         0xb2
  15
  16 #define GP_IO_USE_SEL   0x00
  17 #define GP_IO_SEL       0x04
  18 #define GP_LVL          0x0c
  19 #define GPO_BLINK       0x18
  20 #define GPI_INV         0x2c
  21 #define GP_IO_USE_SEL2  0x30
  22 #define GP_IO_SEL2      0x34
  23 #define GP_LVL2         0x38
  24
  25 #define DEBUG_PERIODIC_SMIS     0
  26
  27 #define MAINBOARD_POWER_OFF     0
  28 #define MAINBOARD_POWER_ON      1
  29 #define MAINBOARD_POWER_KEEP    2
  30
  31 /* D31:F0 LPC bridge */
  32 #define D31F0_ACPI_CNTL         0x44
  33 #define ACPI_CNTL               D31F0_ACPI_CNTL
  34 #define D31F0_GPIO_BASE         0x48
  35 #define D31F0_GPIO_CNTL         0x4c
  36 #define D31F0_PIRQA_ROUT        0x60
  37 #define D31F0_PIRQB_ROUT        0x61
  38 #define D31F0_PIRQC_ROUT        0x62
  39 #define D31F0_PIRQD_ROUT        0x63
  40 #define D31F0_SERIRQ_CNTL       0x64
  41 #define D31F0_PIRQE_ROUT        0x68
  42 #define D31F0_PIRQF_ROUT        0x69
  43 #define D31F0_PIRQG_ROUT        0x6a
  44 #define D31F0_PIRQH_ROUT        0x6b
  45 #define D31F0_LPC_IODEC         0x80
  46 #define D31F0_LPC_EN            0x82
  47 #define   CNF2_LPC_EN           (1 << 13) /* 0x4e/0x4f */
  48 #define   CNF1_LPC_EN           (1 << 12) /* 0x2e/0x2f */
  49 #define   MC_LPC_EN             (1 << 11) /* 0x62/0x66 */
  50 #define   KBC_LPC_EN            (1 << 10) /* 0x60/0x64 */
  51 #define   GAMEH_LPC_EN          (1 << 9)  /* 0x208/0x20f */
  52 #define   GAMEL_LPC_EN          (1 << 8)  /* 0x200/0x207 */
  53 #define   FDD_LPC_EN            (1 << 3)  /* LPC_IO_DEC[12] */
  54 #define   LPT_LPC_EN            (1 << 2)  /* LPC_IO_DEC[9:8] */
  55 #define   COMB_LPC_EN           (1 << 1)  /* LPC_IO_DEC[6:4] */
  56 #define   COMA_LPC_EN           (1 << 0)  /* LPC_IO_DEC[2:0] */
  57 #define D31F0_GEN1_DEC          0x84
  58 #define D31F0_GEN2_DEC          0x88
  59 #define D31F0_GEN3_DEC          0x8c
  60 #define D31F0_GEN4_DEC          0x90
  61 #define D31F0_C5_EXIT_TIMING    0xa8
  62 #define D31F0_CxSTATE_CNF       0xa9
  63 #define D31F0_C4TIMING_CNT      0xaa
  64 #define D31F0_GPIO_ROUT         0xb8
  65
  66 /* D31:F2 SATA */
  67 #define D31F2_IDE_TIM_PRI       0x40
  68 #define D31F2_IDE_TIM_SEC       0x42
  69 #define D31F2_SIDX              0xa0
  70 #define D31F2_SDAT              0xa4
  71
  72 /* D30:F0 PCI-to-PCI bridge */
  73 #define D30F0_SMLT              0x1b
  74
  75 /* D28:F0-5 PCIe root ports */
  76 #define D28Fx_XCAP              0x42
  77 #define D28Fx_SLCAP             0x54
  78
  79 /* PCI Configuration Space (D31:F3): SMBus */
  80 #define SMB_BASE                0x20
  81 #define HOSTC                   0x40
  82
  83 /* HOSTC bits */
  84 #define I2C_EN                  (1 << 2)
  85 #define SMB_SMI_EN              (1 << 1)
  86 #define HST_EN                  (1 << 0)
  87
  88 #define RCBA_V0CTL              0x0014
  89 #define RCBA_V1CAP              0x001c
  90 #define RCBA_V1CTL              0x0020
  91 #define RCBA_V1STS              0x0026
  92 #define RCBA_PAT                0x0030
  93 #define RCBA_CIR1               0x0088
  94 #define RCBA_ESD                0x0104
  95 #define RCBA_ULD                0x0110
  96 #define RCBA_ULBA               0x0118
  97 #define RCBA_LCAP               0x01a4
  98 #define RCBA_LCTL               0x01a8
  99 #define RCBA_LSTS               0x01aa
 100 #define RCBA_CIR2               0x01f4
 101 #define RCBA_CIR3               0x01fc
 102 #define RCBA_BCR                0x0220
 103 #define RCBA_DMIC               0x0234
 104 #define RCBA_RPFN               0x0238
 105 #define RCBA_CIR13              0x0f20
 106 #define RCBA_CIR5               0x1d40
 107 #define RCBA_DMC                0x2010
 108 #define RCBA_CIR6               0x2024
 109 #define RCBA_CIR7               0x2034
 110 #define RCBA_HPTC               0x3404
 111 #define GCS                     0x3410
 112 #define RCBA_BUC                0x3414
 113 #define RCBA_FD                 0x3418 /* Function Disable, see below. */
 114 #define RCBA_CG                 0x341c
 115 #define RCBA_FDSW               0x3420
 116 #define RCBA_CIR8               0x3430
 117 #define RCBA_CIR9               0x350c
 118 #define RCBA_CIR10              0x352c
 119 #define RCBA_MAP                0x35f0 /* UHCI controller #6 remapping */
 120
 121 #define D31IP           0x3100  /* 32bit */
 122 #define D30IP           0x3104  /* 32bit R0: does not generate interrupt */
 123 #define D29IP           0x3108  /* 32bit */
 124 #define D28IP           0x310c  /* 32bit */
 125 #define D27IP           0x3110  /* 32bit */
 126 #define D26IP           0x3114  /* 32bit */
 127 #define D25IP           0x3114  /* 32bit */
 128
 129 #define D31IR           0x3140  /* 16bit */
 130 #define D30IR           0x3142  /* 16bit R0: does not generate interrupt */
 131 #define D29IR           0x3144  /* 16bit */
 132 #define D28IR           0x3146  /* 16bit */
 133 #define D27IR           0x3148  /* 16bit */
 134 #define D26IR           0x314c  /* 16bit */
 135 #define D25IR           0x3150  /* 16bit */
 136 #define OIC             0x31ff  /*  8bit */
 137
 138 #define BUC_LAND        (1 <<  5) /* LAN */
 139 #define FD_SAD2         (1 << 25) /* SATA #2 */
 140 #define FD_TTD          (1 << 24) /* Thermal Throttle */
 141 #define FD_PE6D         (1 << 21) /* PCIe root port 6 */
 142 #define FD_PE5D         (1 << 20) /* PCIe root port 5 */
 143 #define FD_PE4D         (1 << 19) /* PCIe root port 4 */
 144 #define FD_PE3D         (1 << 18) /* PCIe root port 3 */
 145 #define FD_PE2D         (1 << 17) /* PCIe root port 2 */
 146 #define FD_PE1D         (1 << 16) /* PCIe root port 1 */
 147 #define FD_EHCI1D       (1 << 15) /* EHCI #1 */
 148 #define FD_LBD          (1 << 14) /* LPC bridge */
 149 #define FD_EHCI2D       (1 << 13) /* EHCI #2 */
 150 #define FD_U5D          (1 << 12) /* UHCI #5 */
 151 #define FD_U4D          (1 << 11) /* UHCI #4 */
 152 #define FD_U3D          (1 << 10) /* UHCI #3 */
 153 #define FD_U2D          (1 <<  9) /* UHCI #2 */
 154 #define FD_U1D          (1 <<  8) /* UHCI #1 */
 155 #define FD_U6D          (1 <<  7) /* UHCI #6 */
 156 #define FD_HDAD         (1 <<  4) /* HD audio */
 157 #define FD_SD           (1 <<  3) /* SMBus */
 158 #define FD_SAD1         (1 <<  2) /* SATA #1 */
 159
 160 #ifndef __ACPI__
 161
 162 #include <device/pci_ops.h>
 163
 164 void i82801jx_lpc_setup(void);
 165 void i82801jx_setup_bars(void);
 166 void i82801jx_early_init(void);
 167
 168 #endif
 169
 170 #endif