src/southbridge/intel/lynxpoint/acpi/pch.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* Intel Lynx Point PCH support */
   4
   5 #if CONFIG(INTEL_LYNXPOINT_LP)
   6 #define DEFAULT_PRW_VALUE       0x6d
   7 #else
   8 #define DEFAULT_PRW_VALUE       0x0d
   9 #endif
  10
  11 Scope (\)
  12 {
  13         // Root Complex Register Block
  14         OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
  15         Field (RCRB, DWordAcc, Lock, Preserve)
  16         {
  17                 Offset (0x3404), // High Performance Timer Configuration
  18                 HPAS, 2,        // Address Select
  19                 , 5,
  20                 HPTE, 1,        // Address Enable
  21         }
  22 }
  23
  24 // High Definition Audio (Azalia) 0:1b.0
  25 #include "audio.asl"
  26
  27 // PCI Express Ports 0:1c.x
  28 #include <southbridge/intel/common/acpi/pcie.asl>
  29
  30 // USB EHCI 0:1d.0 and 0:1a.0
  31 #include "ehci.asl"
  32
  33 // USB XHCI 0:14.0
  34 #include "xhci.asl"
  35
  36 // LPC Bridge 0:1f.0
  37 #include "lpc.asl"
  38
  39 // SATA 0:1f.2, 0:1f.5
  40 #include "sata.asl"
  41
  42 // SMBus 0:1f.3
  43 #include <southbridge/intel/common/acpi/smbus.asl>
  44
  45 // Serial IO
  46 #if CONFIG(INTEL_LYNXPOINT_LP)
  47 #include "serialio.asl"
  48 #endif
  49
  50 Method (_OSC, 4)
  51 {
  52         /* Check for proper GUID */
  53         If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
  54         {
  55                 /* Let OS control everything */
  56                 Return (Arg3)
  57         }
  58         Else
  59         {
  60                 /* Unrecognized UUID */
  61                 CreateDWordField (Arg3, 0, CDW1)
  62                 CDW1 |= 4
  63                 Return (Arg3)
  64         }
  65 }