src/southbridge/intel/lynxpoint/include/soc/nvs.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H
   4 #define SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H
   5
   6 #include <stdint.h>
   7
   8 struct __packed global_nvs {
   9         /* Miscellaneous */
  10         u16     unused_was_osys; /* 0x00 - Operating System */
  11         u8      smif; /* 0x02 - SMI function call ("TRAP") */
  12         u8      unused_was_prm0; /* 0x03 - SMI function call parameter */
  13         u8      unused_was_prm1; /* 0x04 - SMI function call parameter */
  14         u8      scif; /* 0x05 - SCI function call (via _L00) */
  15         u8      unused_was_prm2; /* 0x06 - SCI function call parameter */
  16         u8      unused_was_prm3; /* 0x07 - SCI function call parameter */
  17         u8      unused_was_lckf; /* 0x08 - Global Lock function for EC */
  18         u8      unused_was_prm4; /* 0x09 - Lock function parameter */
  19         u8      unused_was_prm5; /* 0x0a - Lock function parameter */
  20         u32     p80d; /* 0x0b - Debug port (IO 0x80) value */
  21         u8      lids; /* 0x0f - LID state (open = 1) */
  22         u8      unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
  23         /* Thermal policy */
  24         u8      tlvl; /* 0x11 - Throttle Level Limit */
  25         u8      flvl; /* 0x12 - Current FAN Level */
  26         u8      tcrt; /* 0x13 - Critical Threshold */
  27         u8      tpsv; /* 0x14 - Passive Threshold */
  28         u8      tmax; /* 0x15 - CPU Tj_max */
  29         u8      f0of; /* 0x16 - FAN 0 OFF Threshold */
  30         u8      f0on; /* 0x17 - FAN 0 ON Threshold */
  31         u8      f0pw; /* 0x18 - FAN 0 PWM value */
  32         u8      f1of; /* 0x19 - FAN 1 OFF Threshold */
  33         u8      f1on; /* 0x1a - FAN 1 ON Threshold */
  34         u8      f1pw; /* 0x1b - FAN 1 PWM value */
  35         u8      f2of; /* 0x1c - FAN 2 OFF Threshold */
  36         u8      f2on; /* 0x1d - FAN 2 ON Threshold */
  37         u8      f2pw; /* 0x1e - FAN 2 PWM value */
  38         u8      f3of; /* 0x1f - FAN 3 OFF Threshold */
  39         u8      f3on; /* 0x20 - FAN 3 ON Threshold */
  40         u8      f3pw; /* 0x21 - FAN 3 PWM value */
  41         u8      f4of; /* 0x22 - FAN 4 OFF Threshold */
  42         u8      f4on; /* 0x23 - FAN 4 ON Threshold */
  43         u8      f4pw; /* 0x24 - FAN 4 PWM value */
  44         u8      tmps; /* 0x25 - Temperature Sensor ID */
  45         u8      rsvd3[2];
  46         /* Processor Identification */
  47         u8      unused_was_apic; /* 0x28 - APIC enabled */
  48         u8      unused_was_mpen; /* 0x29 - MP capable/enabled */
  49         u8      pcp0; /* 0x2a - PDC CPU/CORE 0 */
  50         u8      pcp1; /* 0x2b - PDC CPU/CORE 1 */
  51         u8      ppcm; /* 0x2c - Max. PPC state */
  52         u8      unused_was_pcnt; /* 0x2d - Processor Count */
  53         u8      rsvd4[4];
  54         /* Super I/O & CMOS config */
  55         u8      natp; /* 0x32 - SIO type */
  56         u8      s5u0; /* 0x33 - Enable USB0 in S5 */
  57         u8      s5u1; /* 0x34 - Enable USB1 in S5 */
  58         u8      s3u0; /* 0x35 - Enable USB0 in S3 */
  59         u8      s3u1; /* 0x36 - Enable USB1 in S3 */
  60         u8      s33g; /* 0x37 - Enable S3 in 3G */
  61         u32     obsolete_cmem; /* 0x38 - CBMEM TOC */
  62         /* Integrated Graphics Device */
  63         u8      igds; /* 0x3c - IGD state */
  64         u8      tlst; /* 0x3d - Display Toggle List Pointer */
  65         u8      cadl; /* 0x3e - currently attached devices */
  66         u8      padl; /* 0x3f - previously attached devices */
  67         u8      rsvd14[27];
  68         /* TPM support */
  69         u8      tpmp; /* 0x5b - TPM Present */
  70         u8      tpme; /* 0x5c - TPM Enable */
  71         u8      rsvd5[3];
  72         /* LynxPoint Serial IO device BARs */
  73         u32     s0b[8]; /* 0x60 - 0x7f - BAR0 */
  74         u32     s1b[8]; /* 0x80 - 0x9f - BAR1 */
  75         u32     cbmc;   /* 0xa0 - 0xa3 - coreboot memconsole */
  76
  77         /* Required for future unified acpi_save_wake_source. */
  78         u32     pm1i;
  79         u32     gpei;
  80 };
  81
  82 #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */