src/southbridge/intel/lynxpoint/pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/pci_ops.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include "iobp.h"
   8 #include "pch.h"
   9
  10 #ifdef __SIMPLE_DEVICE__
  11 static pci_devfn_t pch_get_lpc_device(void)
  12 {
  13         return PCI_DEV(0, 0x1f, 0);
  14 }
  15 #else
  16 static struct device *pch_get_lpc_device(void)
  17 {
  18         return pcidev_on_root(0x1f, 0);
  19 }
  20 #endif
  21
  22 int pch_silicon_revision(void)
  23 {
  24         static int pch_revision_id = -1;
  25
  26         if (pch_revision_id < 0)
  27                 pch_revision_id = pci_read_config8(pch_get_lpc_device(),
  28                                                    PCI_REVISION_ID);
  29         return pch_revision_id;
  30 }
  31
  32 int pch_silicon_id(void)
  33 {
  34         static int pch_id = -1;
  35
  36         if (pch_id < 0)
  37                 pch_id = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID);
  38
  39         return pch_id;
  40 }
  41
  42 enum pch_platform_type get_pch_platform_type(void)
  43 {
  44         const u16 did = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID);
  45
  46         /* Check if this is a LPT-LP or WPT-LP device ID */
  47         if ((did & 0xff00) == 0x9c00)
  48                 return PCH_TYPE_ULT;
  49
  50         /* Non-LP laptop SKUs have an odd device ID (least significant bit is one) */
  51         if (did & 1)
  52                 return PCH_TYPE_MOBILE;
  53
  54         /* Desktop and Server SKUs have an even device ID */
  55         return PCH_TYPE_DESKTOP;
  56 }
  57
  58 u16 get_pmbase(void)
  59 {
  60         static u16 pmbase;
  61
  62         if (!pmbase)
  63                 pmbase = pci_read_config16(pch_get_lpc_device(),
  64                                            PMBASE) & 0xfffc;
  65         return pmbase;
  66 }
  67
  68 u16 get_gpiobase(void)
  69 {
  70         static u16 gpiobase;
  71
  72         if (!gpiobase)
  73                 gpiobase = pci_read_config16(pch_get_lpc_device(),
  74                                              GPIOBASE) & 0xfffc;
  75         return gpiobase;
  76 }
  77
  78 #ifndef __SIMPLE_DEVICE__
  79
  80 /* Put device in D3Hot Power State */
  81 static void pch_enable_d3hot(struct device *dev)
  82 {
  83         pci_or_config32(dev, PCH_PCS, PCH_PCS_PS_D3HOT);
  84 }
  85
  86 /* Set bit in function disable register to hide this device */
  87 void pch_disable_devfn(struct device *dev)
  88 {
  89         switch (dev->path.pci.devfn) {
  90         case PCI_DEVFN(19, 0): /* Audio DSP */
  91                 RCBA32_OR(FD, PCH_DISABLE_ADSPD);
  92                 break;
  93         case PCI_DEVFN(20, 0): /* XHCI */
  94                 RCBA32_OR(FD, PCH_DISABLE_XHCI);
  95                 break;
  96         case PCI_DEVFN(21, 0): /* DMA */
  97                 pch_enable_d3hot(dev);
  98                 pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0, SIO_IOBP_FUNCDIS_DIS);
  99                 break;
 100         case PCI_DEVFN(21, 1): /* I2C0 */
 101                 pch_enable_d3hot(dev);
 102                 pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0, SIO_IOBP_FUNCDIS_DIS);
 103                 break;
 104         case PCI_DEVFN(21, 2): /* I2C1 */
 105                 pch_enable_d3hot(dev);
 106                 pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0, SIO_IOBP_FUNCDIS_DIS);
 107                 break;
 108         case PCI_DEVFN(21, 3): /* SPI0 */
 109                 pch_enable_d3hot(dev);
 110                 pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0, SIO_IOBP_FUNCDIS_DIS);
 111                 break;
 112         case PCI_DEVFN(21, 4): /* SPI1 */
 113                 pch_enable_d3hot(dev);
 114                 pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0, SIO_IOBP_FUNCDIS_DIS);
 115                 break;
 116         case PCI_DEVFN(21, 5): /* UART0 */
 117                 pch_enable_d3hot(dev);
 118                 pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0, SIO_IOBP_FUNCDIS_DIS);
 119                 break;
 120         case PCI_DEVFN(21, 6): /* UART1 */
 121                 pch_enable_d3hot(dev);
 122                 pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0, SIO_IOBP_FUNCDIS_DIS);
 123                 break;
 124         case PCI_DEVFN(22, 0): /* MEI #1 */
 125                 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
 126                 break;
 127         case PCI_DEVFN(22, 1): /* MEI #2 */
 128                 RCBA32_OR(FD2, PCH_DISABLE_MEI2);
 129                 break;
 130         case PCI_DEVFN(22, 2): /* IDE-R */
 131                 RCBA32_OR(FD2, PCH_DISABLE_IDER);
 132                 break;
 133         case PCI_DEVFN(22, 3): /* KT */
 134                 RCBA32_OR(FD2, PCH_DISABLE_KT);
 135                 break;
 136         case PCI_DEVFN(23, 0): /* SDIO */
 137                 pch_enable_d3hot(dev);
 138                 pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0, SIO_IOBP_FUNCDIS_DIS);
 139                 break;
 140         case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
 141                 RCBA32_OR(BUC, PCH_DISABLE_GBE);
 142                 break;
 143         case PCI_DEVFN(26, 0): /* EHCI #2 */
 144                 RCBA32_OR(FD, PCH_DISABLE_EHCI2);
 145                 break;
 146         case PCI_DEVFN(27, 0): /* HD Audio Controller */
 147                 RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
 148                 break;
 149         case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
 150         case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
 151         case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
 152         case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
 153         case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
 154         case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
 155         case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
 156         case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
 157                 RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
 158                 break;
 159         case PCI_DEVFN(29, 0): /* EHCI #1 */
 160                 RCBA32_OR(FD, PCH_DISABLE_EHCI1);
 161                 break;
 162         case PCI_DEVFN(31, 0): /* LPC */
 163                 RCBA32_OR(FD, PCH_DISABLE_LPC);
 164                 break;
 165         case PCI_DEVFN(31, 2): /* SATA #1 */
 166                 RCBA32_OR(FD, PCH_DISABLE_SATA1);
 167                 break;
 168         case PCI_DEVFN(31, 3): /* SMBUS */
 169                 RCBA32_OR(FD, PCH_DISABLE_SMBUS);
 170                 break;
 171         case PCI_DEVFN(31, 5): /* SATA #2 */
 172                 RCBA32_OR(FD, PCH_DISABLE_SATA2);
 173                 break;
 174         case PCI_DEVFN(31, 6): /* Thermal Subsystem */
 175                 RCBA32_OR(FD, PCH_DISABLE_THERMAL);
 176                 break;
 177         }
 178 }
 179
 180 void pch_enable(struct device *dev)
 181 {
 182         /* PCH PCIe Root Ports are handled in PCIe driver. */
 183         if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT)
 184                 return;
 185
 186         if (!dev->enabled) {
 187                 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
 188
 189                 /* Ensure memory, io, and bus master are all disabled */
 190                 pci_and_config16(dev, PCI_COMMAND,
 191                                 ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 192
 193                 /* Disable this device if possible */
 194                 pch_disable_devfn(dev);
 195         } else {
 196                 /* Enable SERR */
 197                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 198         }
 199 }
 200
 201 struct chip_operations southbridge_intel_lynxpoint_ops = {
 202         CHIP_NAME("Intel Series 8 (Lynx Point) Southbridge")
 203         .enable_dev = pch_enable,
 204 };
 205
 206 #endif /* __SIMPLE_DEVICE__ */