src/southbridge/intel/lynxpoint/pch.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
   4 #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
   5
   6 #include <acpi/acpi.h>
   7 #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */
   8
   9 #define CROS_GPIO_DEVICE_NAME   "LynxPoint"
  10
  11 /*
  12  * Lynx Point PCH PCI Devices:
  13  *
  14  * Bus 0:Device 31:Function 0 LPC Controller1
  15  * Bus 0:Device 31:Function 2 SATA Controller #1
  16  * Bus 0:Device 31:Function 3 SMBus Controller
  17  * Bus 0:Device 31:Function 5 SATA Controller #22
  18  * Bus 0:Device 31:Function 6 Thermal Subsystem
  19  * Bus 0:Device 29:Function 03 USB EHCI Controller #1
  20  * Bus 0:Device 26:Function 03 USB EHCI Controller #2
  21  * Bus 0:Device 28:Function 0 PCI Express* Port 1
  22  * Bus 0:Device 28:Function 1 PCI Express Port 2
  23  * Bus 0:Device 28:Function 2 PCI Express Port 3
  24  * Bus 0:Device 28:Function 3 PCI Express Port 4
  25  * Bus 0:Device 28:Function 4 PCI Express Port 5
  26  * Bus 0:Device 28:Function 5 PCI Express Port 6
  27  * Bus 0:Device 28:Function 6 PCI Express Port 7
  28  * Bus 0:Device 28:Function 7 PCI Express Port 8
  29  * Bus 0:Device 27:Function 0 Intel High Definition Audio Controller
  30  * Bus 0:Device 25:Function 0 Gigabit Ethernet Controller
  31  * Bus 0:Device 22:Function 0 Intel Management Engine Interface #1
  32  * Bus 0:Device 22:Function 1 Intel Management Engine Interface #2
  33  * Bus 0:Device 22:Function 2 IDE-R
  34  * Bus 0:Device 22:Function 3 KT
  35  * Bus 0:Device 20:Function 0 xHCI Controller
  36 */
  37
  38 /* PCH stepping values for LPC device */
  39 #define LPT_H_STEP_B0           0x02
  40 #define LPT_H_STEP_C0           0x03
  41 #define LPT_H_STEP_C1           0x04
  42 #define LPT_H_STEP_C2           0x05
  43 #define LPT_LP_STEP_B0          0x02
  44 #define LPT_LP_STEP_B1          0x03
  45 #define LPT_LP_STEP_B2          0x04
  46
  47 #define SMBUS_SLAVE_ADDR        0x24
  48
  49 #if CONFIG(INTEL_LYNXPOINT_LP)
  50 #define DEFAULT_PMBASE          0x1000
  51 #define DEFAULT_GPIOBASE        0x1400
  52 #define DEFAULT_GPIOSIZE        0x400
  53 #else
  54 #define DEFAULT_PMBASE          0x500
  55 #define DEFAULT_GPIOBASE        0x480
  56 #define DEFAULT_GPIOSIZE        0x80
  57 #endif
  58
  59 #ifndef __ACPI__
  60
  61 #if CONFIG(INTEL_LYNXPOINT_LP)
  62 #define MAX_USB2_PORTS  10
  63 #define MAX_USB3_PORTS  4
  64 #else
  65 #define MAX_USB2_PORTS  14
  66 #define MAX_USB3_PORTS  6
  67 #endif
  68
  69 /* There are 8 OC pins */
  70 #define USB_OC_PIN_SKIP 8
  71
  72 enum usb2_port_location {
  73         USB_PORT_SKIP = 0,
  74         USB_PORT_BACK_PANEL,
  75         USB_PORT_FRONT_PANEL,
  76         USB_PORT_DOCK,
  77         USB_PORT_MINI_PCIE,
  78         USB_PORT_FLEX,
  79         USB_PORT_INTERNAL,
  80 };
  81
  82 /*
  83  * USB port length is in MRC format: binary-coded decimal length in tenths of an inch.
  84  *   4.2 inches -> 0x0042
  85  *  12.7 inches -> 0x0127
  86  */
  87 struct usb2_port_config {
  88         uint16_t length;
  89         bool enable;
  90         unsigned short oc_pin;
  91         enum usb2_port_location location;
  92 };
  93
  94 struct usb3_port_config {
  95         bool enable;
  96         unsigned int oc_pin;
  97 };
  98
  99 /* Mainboard-specific USB configuration */
 100 extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS];
 101 extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS];
 102
 103 static inline int pch_is_lp(void)
 104 {
 105         return CONFIG(INTEL_LYNXPOINT_LP);
 106 }
 107
 108 /* PCH platform types, safe for MRC consumption */
 109 enum pch_platform_type {
 110         PCH_TYPE_MOBILE  = 0,
 111         PCH_TYPE_DESKTOP = 1, /* or server */
 112         PCH_TYPE_ULT     = 5,
 113 };
 114
 115 void pch_dmi_setup_physical_layer(void);
 116 void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
 117 void early_usb_init(void);
 118 void early_thermal_init(void);
 119 void early_pch_init_native(int s3resume);
 120
 121 void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
 122 void usb_ehci_disable(pci_devfn_t dev);
 123 void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
 124 void usb_xhci_route_all(void);
 125
 126 enum pch_platform_type get_pch_platform_type(void);
 127 int pch_silicon_revision(void);
 128 int pch_silicon_id(void);
 129 u16 get_pmbase(void);
 130 u16 get_gpiobase(void);
 131
 132 /* Power Management register handling in pmutil.c */
 133 /* PM1_CNT */
 134 void enable_pm1_control(u32 mask);
 135 void disable_pm1_control(u32 mask);
 136 /* PM1 */
 137 u16 clear_pm1_status(void);
 138 void enable_pm1(u16 events);
 139 u32 clear_smi_status(void);
 140 /* SMI */
 141 void enable_smi(u32 mask);
 142 void disable_smi(u32 mask);
 143 /* ALT_GP_SMI */
 144 u32 clear_alt_smi_status(void);
 145 void enable_alt_smi(u32 mask);
 146 /* TCO */
 147 u32 clear_tco_status(void);
 148 void enable_tco_sci(void);
 149 /* GPE0 */
 150 u32 clear_gpe_status(void);
 151 void clear_gpe_enable(void);
 152 void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4);
 153 void disable_all_gpe(void);
 154 void enable_gpe(u32 mask);
 155 void disable_gpe(u32 mask);
 156
 157 void pch_enable(struct device *dev);
 158 void pch_disable_devfn(struct device *dev);
 159 void pch_log_state(void);
 160 void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
 161
 162 void enable_usb_bar(void);
 163 void early_pch_init(void);
 164 void pch_enable_lpc(void);
 165 void uart_bootblock_init(void);
 166 void mainboard_config_superio(void);
 167 void mainboard_config_rcba(void);
 168
 169 #define MAINBOARD_POWER_OFF     0
 170 #define MAINBOARD_POWER_ON      1
 171 #define MAINBOARD_POWER_KEEP    2
 172
 173 /* PCI Configuration Space (D30:F0): PCI2PCI */
 174 #define PSTS    0x06
 175 #define SMLT    0x1b
 176 #define SECSTS  0x1e
 177 #define INTR    0x3c
 178
 179 /* Power Management Control and Status */
 180 #define PCH_PCS                 0x84
 181 #define  PCH_PCS_PS_D3HOT       3
 182
 183 /* SerialIO */
 184 #define PCH_DEVFN_SDMA          PCI_DEVFN(0x15, 0)
 185 #define PCH_DEVFN_I2C0          PCI_DEVFN(0x15, 1)
 186 #define PCH_DEVFN_I2C1          PCI_DEVFN(0x15, 2)
 187 #define PCH_DEVFN_SPI0          PCI_DEVFN(0x15, 3)
 188 #define PCH_DEVFN_SPI1          PCI_DEVFN(0x15, 4)
 189 #define PCH_DEVFN_UART0         PCI_DEVFN(0x15, 5)
 190 #define PCH_DEVFN_UART1         PCI_DEVFN(0x15, 6)
 191
 192 #define PCH_DEVFN_SDIO          PCI_DEVFN(0x17, 0)
 193
 194 #define PCH_EHCI1_DEV           PCI_DEV(0, 0x1d, 0)
 195 #define PCH_EHCI2_DEV           PCI_DEV(0, 0x1a, 0)
 196 #define PCH_XHCI_DEV            PCI_DEV(0, 0x14, 0)
 197 #define PCH_ME_DEV              PCI_DEV(0, 0x16, 0)
 198 #define PCH_PCIE_DEV_SLOT       28
 199 #define PCH_PCIE_DEV(_func)     PCI_DEV(0, PCH_PCIE_DEV_SLOT, _func)
 200
 201 /* PCI Configuration Space (D31:F0): LPC */
 202 #define PCH_LPC_DEV             PCI_DEV(0, 0x1f, 0)
 203 #define SERIRQ_CNTL             0x64
 204
 205 #define GEN_PMCON_1             0xa0
 206 #define  SMI_LOCK               (1 << 4)
 207 #define GEN_PMCON_2             0xa2
 208 #define  GEN_PMCON_2_DISB       (1 << 7)
 209 #define  GEN_PMCON_2_MEM_SR     (1 << 5)
 210 #define  SYSTEM_RESET_STS       (1 << 4)
 211 #define  THERMTRIP_STS          (1 << 3)
 212 #define  SYSPWR_FLR             (1 << 1)
 213 #define  PWROK_FLR              (1 << 0)
 214 #define GEN_PMCON_3             0xa4
 215 #define  SUS_PWR_FLR            (1 << 14)
 216 #define  GEN_RST_STS            (1 << 9)
 217 #define  RTC_BATTERY_DEAD       (1 << 2)
 218 #define  PWR_FLR                (1 << 1)
 219 #define  SLEEP_AFTER_POWER_FAIL (1 << 0)
 220 #define PMIR                    0xac
 221 #define  PMIR_CF9LOCK           (1 << 31)
 222 #define  PMIR_CF9GR             (1 << 20)
 223 #define  PMIR_XHCI_SMART_AUTO   (1 << 16) /* c.f. LPT BWG or WPT-LP BIOS spec */
 224
 225 /* GEN_PMCON_3 bits */
 226 #define RTC_BATTERY_DEAD        (1 << 2)
 227 #define RTC_POWER_FAILED        (1 << 1)
 228 #define SLEEP_AFTER_POWER_FAIL  (1 << 0)
 229
 230 #define PMBASE                  0x40
 231 #define ACPI_CNTL               0x44
 232 #define   ACPI_EN               (1 << 7)
 233 #define BIOS_CNTL               0xDC
 234 #define GPIO_BASE               0x48 /* LPC GPIO Base Address Register */
 235 #define GPIO_CNTL               0x4C /* LPC GPIO Control Register */
 236 #define GPIO_ROUT               0xb8
 237
 238 #define PIRQA_ROUT              0x60
 239 #define PIRQB_ROUT              0x61
 240 #define PIRQC_ROUT              0x62
 241 #define PIRQD_ROUT              0x63
 242 #define PIRQE_ROUT              0x68
 243 #define PIRQF_ROUT              0x69
 244 #define PIRQG_ROUT              0x6A
 245 #define PIRQH_ROUT              0x6B
 246
 247 #define LPC_IO_DEC              0x80 /* IO Decode Ranges Register */
 248 #define LPC_EN                  0x82 /* LPC IF Enables Register */
 249 #define  CNF2_LPC_EN            (1 << 13) /* 0x4e/0x4f */
 250 #define  CNF1_LPC_EN            (1 << 12) /* 0x2e/0x2f */
 251 #define  MC_LPC_EN              (1 << 11) /* 0x62/0x66 */
 252 #define  KBC_LPC_EN             (1 << 10) /* 0x60/0x64 */
 253 #define  GAMEH_LPC_EN           (1 << 9)  /* 0x208/0x20f */
 254 #define  GAMEL_LPC_EN           (1 << 8)  /* 0x200/0x207 */
 255 #define  FDD_LPC_EN             (1 << 3)  /* LPC_IO_DEC[12] */
 256 #define  LPT_LPC_EN             (1 << 2)  /* LPC_IO_DEC[9:8] */
 257 #define  COMB_LPC_EN            (1 << 1)  /* LPC_IO_DEC[6:4] */
 258 #define  COMA_LPC_EN            (1 << 0)  /* LPC_IO_DEC[2:0] */
 259 #define LPC_IBDF                0x6C /* I/O APIC bus/dev/fn */
 260 #define LPC_HnBDF(n)            (0x70 + (n) * 2) /* HPET n bus/dev/fn */
 261 #define LPC_GEN1_DEC            0x84 /* LPC IF Generic Decode Range 1 */
 262 #define LPC_GEN2_DEC            0x88 /* LPC IF Generic Decode Range 2 */
 263 #define LPC_GEN3_DEC            0x8c /* LPC IF Generic Decode Range 3 */
 264 #define LPC_GEN4_DEC            0x90 /* LPC IF Generic Decode Range 4 */
 265 #define LGMR                    0x98 /* LPC Generic Memory Range */
 266
 267 /* PCI Configuration Space (D31:F2): SATA */
 268 #define PCH_SATA_DEV            PCI_DEV(0, 0x1f, 2)
 269 #define PCH_SATA2_DEV           PCI_DEV(0, 0x1f, 5)
 270
 271 #define IDE_TIM_PRI             0x40    /* IDE timings, primary */
 272 #define   IDE_DECODE_ENABLE     (1 << 15)
 273 #define IDE_TIM_SEC             0x42    /* IDE timings, secondary */
 274
 275 #define SATA_MAP                0x90
 276 #define SATA_PCS                0x92
 277 #define SATA_SCLKG              0x94
 278
 279 #define SATA_SIRI               0xa0 /* SATA Indexed Register Index */
 280 #define SATA_SIRD               0xa4 /* SATA Indexed Register Data */
 281 #define SATA_SP                 0xd0 /* Scratchpad */
 282
 283 /* SATA IOBP Registers */
 284 #define SATA_IOBP_SP0G3IR       0xea000151
 285 #define SATA_IOBP_SP1G3IR       0xea000051
 286 #define SATA_IOBP_SP0DTLE_DATA  0xea002750
 287 #define SATA_IOBP_SP0DTLE_EDGE  0xea002754
 288 #define SATA_IOBP_SP1DTLE_DATA  0xea002550
 289 #define SATA_IOBP_SP1DTLE_EDGE  0xea002554
 290
 291 #define SATA_DTLE_MASK          0xF
 292 #define SATA_DTLE_DATA_SHIFT    24
 293 #define SATA_DTLE_EDGE_SHIFT    16
 294
 295 /*
 296  * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
 297  * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
 298  */
 299 #if CONFIG_USBDEBUG_HCD_INDEX != 2
 300 #define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
 301 #define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
 302 #else
 303 #define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
 304 #define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
 305 #endif
 306
 307 #define PCH_XHCI_TEMP_BAR0      0xe8100000
 308
 309 /* EHCI PCI Registers */
 310 #define EHCI_PWR_CTL_STS        0x54
 311 #define  PWR_CTL_SET_MASK       0x3
 312 #define  PWR_CTL_SET_D0         0x0
 313 #define  PWR_CTL_SET_D3         0x3
 314 #define  PWR_CTL_ENABLE_PME     (1 << 8)
 315 #define  PWR_CTL_STATUS_PME     (1 << 15)
 316 #define EHCI_OCMAP              0x74
 317 #define EHCI_ACCESS_CNTL        0x80
 318 #define  ACCESS_CNTL_ENABLE     (1 << 0)
 319
 320 /* EHCI Memory Registers */
 321 #define EHCI_HCS_PARAMS         0x04
 322 #define EHCI_USB_CMD            0x20
 323 #define  EHCI_USB_CMD_RUN       (1 << 0)
 324 #define  EHCI_USB_CMD_HCRESET   (1 << 1)
 325 #define  EHCI_USB_CMD_PSE       (1 << 4)
 326 #define  EHCI_USB_CMD_ASE       (1 << 5)
 327 #define EHCI_PORTSC(port)       (0x64 + (port) * 4)
 328 #define  EHCI_PORTSC_ENABLED    (1 << 2)
 329 #define  EHCI_PORTSC_SUSPEND    (1 << 7)
 330
 331 /* XHCI PCI Registers */
 332 #define XHCI_PWR_CTL_STS        0x74
 333 #define XHCI_U2OCM1             0xc0
 334 #define XHCI_U2OCM2             0xc4
 335 #define XHCI_U3OCM1             0xc8
 336 #define XHCI_U3OCM2             0xcc
 337 #define XHCI_USB2PR             0xd0
 338 #define XHCI_USB2PRM            0xd4
 339 #define  XHCI_USB2PR_HCSEL      0x7fff
 340 #define XHCI_USB3PR             0xd8
 341 #define  XHCI_USB3PR_SSEN       0x3f
 342 #define XHCI_USB3PRM            0xdc
 343 #define XHCI_USB3FUS            0xe0
 344 #define  XHCI_USB3FUS_SS_MASK   3
 345 #define  XHCI_USB3FUS_SS_SHIFT  3
 346 #define XHCI_USB3PDO            0xe8
 347
 348 /* XHCI Memory Registers */
 349 #define XHCI_HCS_PARAMS_1       0x04
 350 #define XHCI_HCS_PARAMS_2       0x08
 351 #define XHCI_HCS_PARAMS_3       0x0c
 352 #define XHCI_HCC_PARAMS         0x10
 353 #define XHCI_USBCMD             0x80
 354 #define XHCI_USB2_PORTSC(port)  (0x480 + ((port) * 0x10))
 355 #define  XHCI_USB2_PORTSC_WPR   (1 << 31)       /* Warm Port Reset */
 356 #define  XHCI_USB2_PORTSC_CEC   (1 << 23)       /* Port Config Error Change */
 357 #define  XHCI_USB2_PORTSC_PLC   (1 << 22)       /* Port Link State Change */
 358 #define  XHCI_USB2_PORTSC_PRC   (1 << 21)       /* Port Reset Change */
 359 #define  XHCI_USB2_PORTSC_OCC   (1 << 20)       /* Over-current Change */
 360 #define  XHCI_USB2_PORTSC_WRC   (1 << 19)       /* Warm Port Reset Change */
 361 #define  XHCI_USB2_PORTSC_PEC   (1 << 18)       /* Port Enabled Disabled Change */
 362 #define  XHCI_USB2_PORTSC_CSC   (1 << 17)       /* Connect Status Change */
 363 #define  XHCI_USB2_PORTSC_CHST  (0x7f << 17)
 364 #define  XHCI_USB2_PORTSC_LWS   (1 << 16)       /* Port Link State Write Strobe */
 365 #define  XHCI_USB2_PORTSC_PP    (1 <<  9)
 366 #define  XHCI_USB2_PORTSC_PR    (1 <<  4)       /* Port Reset */
 367 #define  XHCI_USB2_PORTSC_PED   (1 <<  1)       /* Port Enable/Disabled */
 368 #define  XHCI_USB2_PORTSC_CCS   (1 <<  0)       /* Current Connect Status */
 369
 370 #define XHCI_USB3_PORTSC(port)  ((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10))
 371 #define  XHCI_USB3_PORTSC_CHST  (0x7f << 17)
 372 #define  XHCI_USB3_PORTSC_WCE   (1 << 25)       /* Wake on Connect */
 373 #define  XHCI_USB3_PORTSC_WDE   (1 << 26)       /* Wake on Disconnect */
 374 #define  XHCI_USB3_PORTSC_WOE   (1 << 27)       /* Wake on Overcurrent */
 375 #define  XHCI_USB3_PORTSC_WRC   (1 << 19)       /* Warm Reset Complete */
 376 #define  XHCI_USB3_PORTSC_LWS   (1 << 16)       /* Link Write Strobe */
 377 #define  XHCI_USB3_PORTSC_PR    (1 << 4)        /* Port Reset */
 378 #define  XHCI_USB3_PORTSC_PED   (1 << 1)        /* Port Enabled/Disabled */
 379 #define  XHCI_USB3_PORTSC_WPR   (1 << 31)       /* Warm Port Reset */
 380 #define  XHCI_USB3_PORTSC_PLS   (0xf << 5)      /* Port Link State */
 381 #define   XHCI_PLSR_DISABLED    (4 << 5)        /* Port is disabled */
 382 #define   XHCI_PLSR_RXDETECT    (5 << 5)        /* Port is disconnected */
 383 #define   XHCI_PLSR_POLLING     (7 << 5)        /* Port is polling */
 384 #define   XHCI_PLSW_ENABLE      (5 << 5)        /* Transition from disabled */
 385
 386 /* Serial IO IOBP Registers */
 387 #define SIO_IOBP_PORTCTRL0      0xcb000000      /* SDIO D23:F0 */
 388 #define  SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN         (1 << 5)
 389 #define  SIO_IOBP_PORTCTRL0_PCI_CONF_DIS        (1 << 4)
 390 #define SIO_IOBP_PORTCTRL1      0xcb000014      /* SDIO D23:F0 */
 391 #define  SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x)     (((x) & 3) << 13)
 392 #define SIO_IOBP_GPIODF         0xcb000154
 393 #define  SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN       (1 << 4)
 394 #define  SIO_IOBP_GPIODF_DMA_IDLE_DET_EN        (1 << 3)
 395 #define  SIO_IOBP_GPIODF_UART_IDLE_DET_EN       (1 << 2)
 396 #define  SIO_IOBP_GPIODF_I2C_IDLE_DET_EN        (1 << 1)
 397 #define  SIO_IOBP_GPIODF_SPI_IDLE_DET_EN        (1 << 0)
 398 #define SIO_IOBP_PORTCTRL2      0xcb000240      /* DMA D21:F0 */
 399 #define SIO_IOBP_PORTCTRL3      0xcb000248      /* I2C0 D21:F1 */
 400 #define SIO_IOBP_PORTCTRL4      0xcb000250      /* I2C1 D21:F2 */
 401 #define SIO_IOBP_PORTCTRL5      0xcb000258      /* SPI0 D21:F3 */
 402 #define SIO_IOBP_PORTCTRL6      0xcb000260      /* SPI1 D21:F4 */
 403 #define SIO_IOBP_PORTCTRL7      0xcb000268      /* UART0 D21:F5 */
 404 #define SIO_IOBP_PORTCTRL8      0xcb000270      /* UART1 D21:F6 */
 405 #define SIO_IOBP_PORTCTRLX(x)   (0xcb000240 + ((x) * 8))
 406 /* PORTCTRL 2-8 have the same layout */
 407 #define  SIO_IOBP_PORTCTRL_ACPI_IRQ_EN          (1 << 21)
 408 #define  SIO_IOBP_PORTCTRL_PCI_CONF_DIS         (1 << 20)
 409 #define  SIO_IOBP_PORTCTRL_SNOOP_SELECT(x)      (((x) & 3) << 18)
 410 #define  SIO_IOBP_PORTCTRL_INT_PIN(x)           (((x) & 0xf) << 2)
 411 #define  SIO_IOBP_PORTCTRL_PM_CAP_PRSNT         (1 << 1)
 412 #define SIO_IOBP_FUNCDIS0       0xce00aa07      /* DMA D21:F0 */
 413 #define SIO_IOBP_FUNCDIS1       0xce00aa47      /* I2C0 D21:F1 */
 414 #define SIO_IOBP_FUNCDIS2       0xce00aa87      /* I2C1 D21:F2 */
 415 #define SIO_IOBP_FUNCDIS3       0xce00aac7      /* SPI0 D21:F3 */
 416 #define SIO_IOBP_FUNCDIS4       0xce00ab07      /* SPI1 D21:F4 */
 417 #define SIO_IOBP_FUNCDIS5       0xce00ab47      /* UART0 D21:F5 */
 418 #define SIO_IOBP_FUNCDIS6       0xce00ab87      /* UART1 D21:F6 */
 419 #define SIO_IOBP_FUNCDIS7       0xce00ae07      /* SDIO D23:F0 */
 420 #define  SIO_IOBP_FUNCDIS_DIS                   (1 << 8)
 421
 422 /* Serial IO Devices */
 423 #define SIO_ID_SDMA             0 /* D21:F0 */
 424 #define SIO_ID_I2C0             1 /* D21:F1 */
 425 #define SIO_ID_I2C1             2 /* D21:F2 */
 426 #define SIO_ID_SPI0             3 /* D21:F3 */
 427 #define SIO_ID_SPI1             4 /* D21:F4 */
 428 #define SIO_ID_UART0            5 /* D21:F5 */
 429 #define SIO_ID_UART1            6 /* D21:F6 */
 430 #define SIO_ID_SDIO             7 /* D23:F0 */
 431
 432 #define SIO_REG_PPR_CLOCK               0x800
 433 #define  SIO_REG_PPR_CLOCK_EN            (1 << 0)
 434 #define  SIO_REG_PPR_CLOCK_UPDATE        (1 << 31)
 435 #define  SIO_REG_PPR_CLOCK_M_DIV         0x25a
 436 #define  SIO_REG_PPR_CLOCK_N_DIV         0x7fff
 437 #define SIO_REG_PPR_RST                 0x804
 438 #define  SIO_REG_PPR_RST_ASSERT          0x3
 439 #define SIO_REG_PPR_GEN                 0x808
 440 #define  SIO_REG_PPR_GEN_LTR_MODE_MASK   (1 << 2)
 441 #define  SIO_REG_PPR_GEN_VOLTAGE_MASK    (1 << 3)
 442 #define  SIO_REG_PPR_GEN_VOLTAGE(x)      (((x) & 1) << 3)
 443 #define SIO_REG_AUTO_LTR                0x814
 444
 445 #define SIO_REG_SDIO_PPR_GEN            0x1008
 446 #define SIO_REG_SDIO_PPR_SW_LTR         0x1010
 447 #define SIO_REG_SDIO_PPR_CMD12          0x3c
 448 #define  SIO_REG_SDIO_PPR_CMD12_B30      (1 << 30)
 449
 450 #define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
 451 #define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
 452 #define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */
 453 #define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */
 454
 455 /* PCI Configuration Space (D31:F3): SMBus */
 456 #define PCH_SMBUS_DEV           PCI_DEV(0, 0x1f, 3)
 457 #define SMB_BASE                0x20
 458 #define HOSTC                   0x40
 459
 460 /* HOSTC bits */
 461 #define I2C_EN                  (1 << 2)
 462 #define SMB_SMI_EN              (1 << 1)
 463 #define HST_EN                  (1 << 0)
 464
 465 /* Southbridge IO BARs */
 466
 467 #define PMBASE                  0x40
 468 #define GPIOBASE                0x48
 469
 470 #define CIR0050         0x0050  /* 32bit */
 471
 472 #define RPC             0x0400  /* 32bit */
 473 #define RPFN            0x0404  /* 32bit */
 474
 475 /* Root Port configuratinon space hide */
 476 #define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
 477 /* Get the function number assigned to a Root Port */
 478 #define RPFN_FNGET(reg,port)    (((reg) >> ((port) * 4)) & 7)
 479 /* Set the function number for a Root Port */
 480 #define RPFN_FNSET(port,func)   (((func) & 7) << ((port) * 4))
 481 /* Root Port function number mask */
 482 #define RPFN_FNMASK(port)       (7 << ((port) * 4))
 483
 484 #define TRSR            0x1e00  /*  8bit */
 485 #define TRCR            0x1e10  /* 64bit */
 486 #define TWDR            0x1e18  /* 64bit */
 487
 488 #define IOTR0           0x1e80  /* 64bit */
 489 #define IOTR1           0x1e88  /* 64bit */
 490 #define IOTR2           0x1e90  /* 64bit */
 491 #define IOTR3           0x1e98  /* 64bit */
 492
 493 #define V0CTL           0x2014  /* 32bit */
 494 #define V0STS           0x201a  /* 16bit */
 495
 496 #define V1CTL           0x2020  /* 32bit */
 497 #define V1STS           0x2026  /* 16bit */
 498
 499 #define VPCTL           0x2030  /* 32bit */
 500 #define VPSTS           0x2038  /* 16bit */
 501
 502 #define VMCTL           0x2040  /* 32bit */
 503 #define VMSTS           0x2048  /* 16bit */
 504
 505 #define DLCTL2          0x21b0
 506
 507 #define TCTL            0x3000  /*  8bit */
 508
 509 #define NOINT           0
 510 #define INTA            1
 511 #define INTB            2
 512 #define INTC            3
 513 #define INTD            4
 514
 515 #define DIR_IDR         12      /* Interrupt D Pin Offset */
 516 #define DIR_ICR         8       /* Interrupt C Pin Offset */
 517 #define DIR_IBR         4       /* Interrupt B Pin Offset */
 518 #define DIR_IAR         0       /* Interrupt A Pin Offset */
 519
 520 #define PIRQA           0
 521 #define PIRQB           1
 522 #define PIRQC           2
 523 #define PIRQD           3
 524 #define PIRQE           4
 525 #define PIRQF           5
 526 #define PIRQG           6
 527 #define PIRQH           7
 528
 529 /* IO Buffer Programming */
 530 #define IOBPIRI         0x2330
 531 #define IOBPD           0x2334
 532 #define IOBPS           0x2338
 533 #define  IOBPS_READY    0x0001
 534 #define  IOBPS_TX_MASK  0x0006
 535 #define  IOBPS_MASK     0xff00
 536 #define  IOBPS_READ     0x0600
 537 #define  IOBPS_WRITE    0x0700
 538 #define IOBPU           0x233a
 539 #define  IOBPU_MAGIC    0xf000
 540 #define  IOBP_PCICFG_READ       0x0400
 541 #define  IOBP_PCICFG_WRITE      0x0500
 542
 543 #define D31IP           0x3100  /* 32bit */
 544 #define D31IP_TTIP      24      /* Thermal Throttle Pin */
 545 #define D31IP_SIP2      20      /* SATA Pin 2 */
 546 #define D31IP_SMIP      12      /* SMBUS Pin */
 547 #define D31IP_SIP       8       /* SATA Pin */
 548 #define D30IP           0x3104  /* 32bit */
 549 #define D30IP_PIP       0       /* PCI Bridge Pin */
 550 #define D29IP           0x3108  /* 32bit */
 551 #define D29IP_E1P       0       /* EHCI #1 Pin */
 552 #define D28IP           0x310c  /* 32bit */
 553 #define D28IP_P8IP      28      /* PCI Express Port 8 */
 554 #define D28IP_P7IP      24      /* PCI Express Port 7 */
 555 #define D28IP_P6IP      20      /* PCI Express Port 6 */
 556 #define D28IP_P5IP      16      /* PCI Express Port 5 */
 557 #define D28IP_P4IP      12      /* PCI Express Port 4 */
 558 #define D28IP_P3IP      8       /* PCI Express Port 3 */
 559 #define D28IP_P2IP      4       /* PCI Express Port 2 */
 560 #define D28IP_P1IP      0       /* PCI Express Port 1 */
 561 #define D27IP           0x3110  /* 32bit */
 562 #define D27IP_ZIP       0       /* HD Audio Pin */
 563 #define D26IP           0x3114  /* 32bit */
 564 #define D26IP_E2P       0       /* EHCI #2 Pin */
 565 #define D25IP           0x3118  /* 32bit */
 566 #define D25IP_LIP       0       /* GbE LAN Pin */
 567 #define D22IP           0x3124  /* 32bit */
 568 #define D22IP_KTIP      12      /* KT Pin */
 569 #define D22IP_IDERIP    8       /* IDE-R Pin */
 570 #define D22IP_MEI2IP    4       /* MEI #2 Pin */
 571 #define D22IP_MEI1IP    0       /* MEI #1 Pin */
 572 #define D20IP           0x3128  /* 32bit */
 573 #define D20IP_XHCI      0       /* XHCI Pin */
 574 #define D31IR           0x3140  /* 16bit */
 575 #define D30IR           0x3142  /* 16bit */
 576 #define D29IR           0x3144  /* 16bit */
 577 #define D28IR           0x3146  /* 16bit */
 578 #define D27IR           0x3148  /* 16bit */
 579 #define D26IR           0x314c  /* 16bit */
 580 #define D25IR           0x3150  /* 16bit */
 581 #define D23IR           0x3158  /* 16bit */
 582 #define D22IR           0x315c  /* 16bit */
 583 #define D20IR           0x3160  /* 16bit */
 584 #define D21IR           0x3164  /* 16bit */
 585 #define D19IR           0x3168  /* 16bit */
 586 #define ACPIIRQEN       0x31e0  /* 32bit */
 587 #define OIC             0x31fe  /* 16bit */
 588 #define PRSTS           0x3310  /* 32bit */
 589 #define PMSYNC_CONFIG   0x33c4  /* 32bit */
 590 #define PMSYNC_CONFIG2  0x33cc  /* 32bit */
 591 #define SOFT_RESET_CTRL 0x38f4
 592 #define SOFT_RESET_DATA 0x38f8
 593
 594 #define DIR_ROUTE(a,b,c,d) \
 595   (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
 596   ((b) << DIR_IBR) | ((a) << DIR_IAR))
 597
 598 #define RC              0x3400  /* 32bit */
 599 #define HPTC            0x3404  /* 32bit */
 600 #define GCS             0x3410  /* 32bit */
 601 #define BUC             0x3414  /* 32bit */
 602 #define PCH_DISABLE_GBE         (1 << 5)
 603 #define FD              0x3418  /* 32bit */
 604 #define DISPBDF         0x3424  /* 16bit */
 605 #define FD2             0x3428  /* 32bit */
 606 #define CG              0x341c  /* 32bit */
 607
 608 /* Function Disable 1 RCBA 0x3418 */
 609 #define PCH_DISABLE_ALWAYS      (1 << 0)
 610 #define PCH_DISABLE_ADSPD       (1 << 1)
 611 #define PCH_DISABLE_SATA1       (1 << 2)
 612 #define PCH_DISABLE_SMBUS       (1 << 3)
 613 #define PCH_DISABLE_HD_AUDIO    (1 << 4)
 614 #define PCH_DISABLE_EHCI2       (1 << 13)
 615 #define PCH_DISABLE_LPC         (1 << 14)
 616 #define PCH_DISABLE_EHCI1       (1 << 15)
 617 #define PCH_DISABLE_PCIE(x)     (1 << (16 + (x)))
 618 #define PCH_DISABLE_THERMAL     (1 << 24)
 619 #define PCH_DISABLE_SATA2       (1 << 25)
 620 #define PCH_DISABLE_XHCI        (1 << 27)
 621
 622 /* Function Disable 2 RCBA 0x3428 */
 623 #define PCH_DISABLE_KT          (1 << 4)
 624 #define PCH_DISABLE_IDER        (1 << 3)
 625 #define PCH_DISABLE_MEI2        (1 << 2)
 626 #define PCH_DISABLE_MEI1        (1 << 1)
 627 #define PCH_ENABLE_DBDF         (1 << 0)
 628
 629 #define PCH_IOAPIC_PCI_BUS      250
 630 #define PCH_IOAPIC_PCI_SLOT     31
 631 #define PCH_HPET_PCI_BUS        250
 632 #define PCH_HPET_PCI_SLOT       15
 633
 634 /* ICH7 PMBASE */
 635 #define PM1_STS         0x00
 636 #define   WAK_STS       (1 << 15)
 637 #define   PCIEXPWAK_STS (1 << 14)
 638 #define   PRBTNOR_STS   (1 << 11)
 639 #define   RTC_STS       (1 << 10)
 640 #define   PWRBTN_STS    (1 << 8)
 641 #define   GBL_STS       (1 << 5)
 642 #define   BM_STS        (1 << 4)
 643 #define   TMROF_STS     (1 << 0)
 644 #define PM1_EN          0x02
 645 #define   PCIEXPWAK_DIS (1 << 14)
 646 #define   RTC_EN        (1 << 10)
 647 #define   PWRBTN_EN     (1 << 8)
 648 #define   GBL_EN        (1 << 5)
 649 #define   TMROF_EN      (1 << 0)
 650 #define PM1_CNT         0x04
 651 #define   GBL_RLS       (1 << 2)
 652 #define   BM_RLD        (1 << 1)
 653 #define   SCI_EN        (1 << 0)
 654 #define PM1_TMR         0x08
 655 #define PROC_CNT        0x10
 656 #define LV2             0x14
 657 #define LV3             0x15
 658 #define LV4             0x16
 659 #define GPE0_STS        0x20
 660 #define   PME_B0_STS    (1 << 13)
 661 #define   PME_STS       (1 << 11)
 662 #define   BATLOW_STS    (1 << 10)
 663 #define   PCI_EXP_STS   (1 << 9)
 664 #define   RI_STS        (1 << 8)
 665 #define   SMB_WAK_STS   (1 << 7)
 666 #define   TCOSCI_STS    (1 << 6)
 667 #define   SWGPE_STS     (1 << 2)
 668 #define   HOT_PLUG_STS  (1 << 1)
 669 #define GPE0_STS_2      0x24
 670 #define GPE0_EN         0x28
 671 #define   PME_B0_EN     (1 << 13)
 672 #define   PME_EN        (1 << 11)
 673 #define   TCOSCI_EN     (1 << 6)
 674 #define GPE0_EN_2       0x2c
 675 #define SMI_EN          0x30
 676 #define   INTEL_USB2_EN  (1 << 18) // Intel-Specific USB2 SMI logic
 677 #define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
 678 #define   PERIODIC_EN    (1 << 14) // SMI on PERIODIC_STS in SMI_STS
 679 #define   TCO_EN         (1 << 13) // Enable TCO Logic (BIOSWE et al)
 680 #define   MCSMI_EN       (1 << 11) // Trap microcontroller range access
 681 #define   BIOS_RLS       (1 <<  7) // asserts SCI on bit set
 682 #define   SWSMI_TMR_EN   (1 <<  6) // start software smi timer on bit set
 683 #define   APMC_EN        (1 <<  5) // Writes to APM_CNT cause SMI#
 684 #define   SLP_SMI_EN     (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
 685 #define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
 686 #define   BIOS_EN        (1 <<  2) // Assert SMI# on setting GBL_RLS bit
 687 #define   EOS            (1 <<  1) // End of SMI (deassert SMI#)
 688 #define   GBL_SMI_EN     (1 <<  0) // SMI# generation at all?
 689 #define SMI_STS         0x34
 690 #define ALT_GP_SMI_EN   0x38
 691 #define ALT_GP_SMI_STS  0x3a
 692 #define GPE_CNTL        0x42
 693 #define DEVACT_STS      0x44
 694 #define PM2_CNT         0x50 // mobile only
 695 #define C3_RES          0x54
 696
 697 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
 698 #define TCO1_STS        0x64
 699 #define   DMISCI_STS    (1 << 9)
 700 #define TCO2_STS        0x66
 701 #define   TCO2_STS_SECOND_TO    (1 << 1)
 702 #endif
 703
 704 #define ALT_GP_SMI_EN2  0x5c
 705 #define ALT_GP_SMI_STS2 0x5e
 706
 707 /* Lynxpoint LP */
 708 #define LP_GPE0_STS_1   0x80    /* GPIO 0-31 */
 709 #define LP_GPE0_STS_2   0x84    /* GPIO 32-63 */
 710 #define LP_GPE0_STS_3   0x88    /* GPIO 64-94 */
 711 #define LP_GPE0_STS_4   0x8c    /* Standard GPE */
 712 #define LP_GPE0_EN_1    0x90
 713 #define LP_GPE0_EN_2    0x94
 714 #define LP_GPE0_EN_3    0x98
 715 #define LP_GPE0_EN_4    0x9c
 716
 717 /*
 718  * SPI Opcode Menu setup for SPIBAR lockdown
 719  * should support most common flash chips.
 720  */
 721
 722 #define SPIBAR_OFFSET 0x3800
 723 #define SPIBAR8(x) RCBA8((x) + SPIBAR_OFFSET)
 724 #define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET)
 725 #define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET)
 726
 727 /* Registers within the SPIBAR */
 728 #define SSFC 0x91
 729 #define FDOC 0xb0
 730 #define FDOD 0xb4
 731
 732 #define SPIBAR_HSFS                 0x3804   /* SPI hardware sequence status */
 733 #define  SPIBAR_HSFS_SCIP           (1 << 5) /* SPI Cycle In Progress */
 734 #define  SPIBAR_HSFS_AEL            (1 << 2) /* SPI Access Error Log */
 735 #define  SPIBAR_HSFS_FCERR          (1 << 1) /* SPI Flash Cycle Error */
 736 #define  SPIBAR_HSFS_FDONE          (1 << 0) /* SPI Flash Cycle Done */
 737 #define SPIBAR_HSFC                 0x3806   /* SPI hardware sequence control */
 738 #define  SPIBAR_HSFC_BYTE_COUNT(c)  ((((c) - 1) & 0x3f) << 8)
 739 #define  SPIBAR_HSFC_CYCLE_READ     (0 << 1) /* Read cycle */
 740 #define  SPIBAR_HSFC_CYCLE_WRITE    (2 << 1) /* Write cycle */
 741 #define  SPIBAR_HSFC_CYCLE_ERASE    (3 << 1) /* Erase cycle */
 742 #define  SPIBAR_HSFC_GO             (1 << 0) /* GO: start SPI transaction */
 743 #define SPIBAR_FADDR                0x3808   /* SPI flash address */
 744 #define SPIBAR_FDATA(n)             (0x3810 + (4 * (n))) /* SPI flash data */
 745
 746 #endif /* __ACPI__ */
 747 #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */