| blob | b7bd55814555fc7bc369ad60b3b9e82d53c804db |
1 /* SPDX-License-Identifier: GPL-2.0-only */
15 ));
16 }
25 PRESENT_DEC, {
27 }},
30 }},
31 /* FIXME: This MSR not documented for Nehalem */
33 /* This field indicates the intended scalable bus clock speed */
35 }},
40 }},
46 }},
51 }},
54 /* The is ratio of the frequency that invariant TSC runs at. The invariant
55 * TSC requency can be computed by multipying this ratio by 133.33 Mhz
56 */
58 }},
61 }},
64 }},
65 /* FIXME: There is already two 0x1ad MSRs for Nehalem in the
66 * Intel 64 and IA-32 Architectures Software Developer's Manual
67 * Volume 3C 34-91. But from decimal value of this register,
68 * we can conclude, that it was just typo, and this register
69 * have address 0x1ac.
70 */
77 }},
79 /* TDC Limit in 1/8 Amp granularity */
81 }},
86 }},
88 /* TDP Limit in 1/8 Watt granularity */
90 }},
92 }},
95 // "RO" if MSR_PLATFORM_INFO.[28] = 0
96 // "RW" if MSR_PLATFORM_INFO.[23] = 1
99 // Maximum Turbo Ratio Limit of 4 core active
101 }},
103 // Maximum Turbo Ratio Limit of 3 core active
105 }},
107 // Maximum Turbo Ratio Limit of 2 core active
109 }},
111 // Maximum Turbo Ratio Limit of 1 core active
113 }},
115 }},
120 }},
124 }},
126 }},
131 }},
135 }},
137 }},
142 }},
146 }},
148 }},
153 }},
157 }},
159 }},
164 }},
168 }},
170 }},
173 /* Value since last reset that this package is in C3 states.
174 * Count at the same frequency as the TSC.
175 */
177 }},
179 }},
182 }},
185 }},
188 }},
191 }},
194 }},
197 }},
200 }},
203 }},
206 }},
209 }},
212 }},
215 }},
218 }},
221 }},
223 /* ==========================================================================
224 * Per core MSRs
225 * ==========================================================================
226 */
231 }},
235 }},
238 }},
241 }},
243 /* In Intel's manual there is MAXPHYWID,
244 * which determine index of highest bit of
245 * APIC Base itself, so marking it as
246 * 'RESERVED'.
247 */
251 }},
256 }},
260 }},
263 }},
268 }},
270 }},
271 /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */
275 /* if CPUID.01H: ECX[6] = 1 */
280 }},
281 /* if CPUID.01H: ECX[6] = 1 */
284 }},
286 /* if CPUID.01H: ECX[5 or 6] = 1 */
288 /* This bit enables VMX for system executive
289 * that do not require SMX.
290 */
294 }},
296 /* This bit enables a system executive to use
297 * VMX in conjunction with SMX to support Intel
298 * Trusted Execution Technology.
299 */
303 }},
304 /* if CPUID.01H: ECX[5 or 6] = 1 */
306 /* Once the Lock bit is set, the contents
307 * of this register cannot be modified.
308 * Therefore the lock bit must be set after
309 * configuring support for Intel Virtualization
310 * Technology and prior transferring control
311 * to an Option ROM or bootloader. Hence, once
312 * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR
313 * contents are preserved across RESET when
314 * PWRGOOD it not deasserted.
315 */
319 }},
321 }},
324 }},
327 }},
330 }},
333 }},
336 }},
339 }},
342 }},
345 }},
349 }},
353 }},
356 }},
359 }},
363 }},
367 }},
371 }},
375 }},
383 }},
388 }},
395 }},
403 }},
408 "IO register specified by MSR_PMG_IO_CAPTURE_BASE "
411 }},
414 /* Specifies the lowest processor specific C-state code name
415 * (consuming the least power) for the package. The default is set
416 * as factory-configured package C-state limit.
417 */
427 /* Note: this field cannot be used to limit
428 * package C-state to C3
429 */
430 }},
432 }},
437 /* Specifies the encoding value of the maximum C-State code name
438 * to be included when IO read to MWAIT redirection is enabled by
439 * MSR_PMG_CST_CONFIG_CONTROL[bit10].
440 */
445 }},
447 /* Specifies the base address visible to software for IO redirection.
448 * If I/O MWAIT Redirection is enabled, reads to this address will be
449 * consumed by the power management logic and decoded to MWAIT
450 * instructions. When IO port address redirection is enabled,
451 * this is the I/O port address reported to the OS/software.
452 */
454 }},
456 }},
459 }},
462 }},
465 }},
468 }},
471 }},
474 }},
477 }},
481 /* When set, bit indicates that a machine check has been
482 * generated. If a second machine check is detected while
483 * this bit is still set, the processor enters a shutdown state.
484 * Software should write this bit to 0 after processing
485 * a machine check exception.
486 */
490 }},
492 /* When set, bit indicates that the instruction addressed
493 * by the instruction pointer pushed on the stack (when
494 * the machine check was generated) is directly associated
495 * with the error
496 */
500 }},
502 /* When set, bit indicates that the instruction addressed
503 * by the instruction pointer pushed on the stack (when
504 * the machine check was generated) can be used to restart
505 * the program. If cleared, the program cannot be reliably restarted
506 */
510 }},
512 }},
513 /* if CPUID.0AH: EAX[15:8] > 0 */
518 /* When CMASK is not zero, the corresponding performance
519 * counter 0 increments each cycle if the event count
520 * is greater than or equal to the CMASK.
521 */
523 }},
528 }},
533 }},
536 }},
541 }},
546 }},
551 }},
556 }},
561 }},
563 /* Qualifies the microarchitectural condition
564 * to detect on the selected event logic. */
566 }},
568 /* Selects a performance event logic unit. */
570 }},
572 }},
573 /* if CPUID.0AH: EAX[15:8] > 0 */
578 /* When CMASK is not zero, the corresponding performance
579 * counter 1 increments each cycle if the event count
580 * is greater than or equal to the CMASK.
581 */
583 }},
588 }},
593 }},
596 }},
601 }},
606 }},
611 }},
616 }},
621 }},
623 /* Qualifies the microarchitectural condition
624 * to detect on the selected event logic. */
626 }},
628 /* Selects a performance event logic unit. */
630 }},
632 }},
633 /* if CPUID.0AH: EAX[15:8] > 0 */
638 /* When CMASK is not zero, the corresponding performance
639 * counter 2 increments each cycle if the event count
640 * is greater than or equal to the CMASK.
641 */
643 }},
648 }},
653 }},
656 }},
661 }},
666 }},
671 }},
676 }},
681 }},
683 /* Qualifies the microarchitectural condition
684 * to detect on the selected event logic. */
686 }},
688 /* Selects a performance event logic unit. */
690 }},
692 }},
693 /* if CPUID.0AH: EAX[15:8] > 0 */
698 /* When CMASK is not zero, the corresponding performance
699 * counter 3 increments each cycle if the event count
700 * is greater than or equal to the CMASK.
701 */
703 }},
708 }},
713 }},
716 }},
721 }},
726 }},
731 }},
736 }},
741 }},
743 /* Qualifies the microarchitectural condition
744 * to detect on the selected event logic. */
746 }},
748 /* Selects a performance event logic unit. */
750 }},
752 }},
757 }},
759 }},
762 }},
770 }},
773 }},
776 }},
780 }},
784 }},
787 }},
791 /* Note: [38] bit using for whole package,
792 * while some other bits can be Core or Thread
793 * specific.
794 */
796 /* When set to a 0 on processors that support IDA,
797 * CPUID.06H: EAX[1] reports the processor's
798 * support of turbo mode is enabled.
799 */
801 /* When set 1 on processors that support Intel Turbo Boost
802 * technology, the turbo mode feature is disabled and
803 * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
804 */
807 /* Note: the power-on default value is used by BIOS to detect
808 * hardware support of turbo mode. If power-on default value is 1,
809 * turbo mode is available in the processor. If power-on default
810 * value is 0, turbo mode not available.
811 */
812 }},
816 }},
820 }},
823 }},
827 }},
830 }},
831 /* Note: [16] bit using for whole package,
832 * while some other bits can be Core or Thread
833 * specific.
834 */
836 PRESENT_BIN, {
838 }},
841 PRESENT_BIN, {
843 }},
846 }},
850 }},
855 }},
859 }},
861 }},
865 /* The minimum temperature at which PROCHOT# will be
866 * asserted. The value in degree C.
867 */
869 }},
872 }},
876 }},
880 /* This bit status is also reflected
881 * by CPUID.(EAX=06h):ECX[3]
882 */
888 }},
895 }},
897 }},
900 /* "Nehalem support filtering of LBR based on combination of CPL
901 * and branch type conditions. When LBR filtering is enabled,
902 * the LBR stack only captures the subset of branches
903 * that are specified by MSR_LBR_SELECT."
904 *
905 * -- Section 17.6.2 of Intel 64 and IA-32 Architectures Software
906 * Developer's Manual, Volume 3
907 */
909 }},
912 /* Contains an index (bits 0-3) that points to the MSR containing
913 * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680).
914 */
916 }},
919 /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */
921 /* Only if IA32_PERF_CAPABILITIES[12] = 1 */
926 }},
932 }},
933 /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
939 }},
940 /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
945 }},
950 }},
955 }},
961 }},
968 }},
973 }},
980 }},
986 }},
988 }},
991 /* Contains a pointer to the last branch instruction
992 * that the processor executed prior to the last exception
993 * that was generated or the last interrupt that was handled.
994 */
996 }},
999 /* This area contains a pointer to the target of the
1000 * last branch instruction that the processor executed
1001 * prior to the last exception that was generated or
1002 * the last interrupt that was handled
1003 */
1005 }},
1008 /* Base address of SMM memory range.
1009 * Writeable only in SMM, so marking it as read-only */
1013 }},
1017 }},
1019 }},
1022 /* Range Mask of SMM memory range.
1023 * Writeable only in SMM, so marking it as read-only */
1027 }},
1032 }},
1035 }},
1039 }},
1042 /* If set, CPU supports Prefetch-Hint type.
1043 * TODO: As it is undocumented, which bit (or bits)
1044 * are needed to "be set", we need collect some
1045 * outputs of msrtool to understand possible msr values.
1046 */
1048 }},
1051 /* This register defined as introduced only
1052 * in 06_2EH Nehalem model (latest), so be careful!
1053 */
1056 /* Hardware block of DCA */
1060 }},
1063 /* Software block of DCA */
1067 }},
1070 /* Writes will update the register
1071 * but have no HW side-effect */
1073 }},
1077 }},
1080 }},
1083 }},
1085 /* Set by HW when DCA is fuse-enabled and
1086 * no defeauteres are set */
1090 }},
1092 }},
1096 /* Whole package bit */
1100 "SpeedStep Technology operating point when all "
1103 }},
1106 }},
1109 }},
1112 }},
1115 }},
1118 }},
1121 }},
1124 }},
1127 }},
1130 }},
1133 }},
1136 }},
1139 }},
1142 }},
1145 }},
1148 }},
1151 }},
1154 }},
1155 /* if IA32_MTRR_CAP[7:0] > 8 */
1158 }},
1159 /* if IA32_MTRR_CAP[7:0] > 8 */
1162 }},
1163 /* if IA32_MTRR_CAP[7:0] > 9 */
1166 }},
1167 /* if IA32_MTRR_CAP[7:0] > 9 */
1170 }},
1173 }},
1176 }},
1179 }},
1182 }},
1185 }},
1188 }},
1191 }},
1194 }},
1197 }},
1200 }},
1203 }},
1208 }},
1212 }},
1216 }},
1220 }},
1224 }},
1228 }},
1232 }},
1236 }},
1238 }},
1243 }},
1247 }},
1249 }},
1254 }},
1258 }},
1260 }},
1265 }},
1269 }},
1271 }},
1276 }},
1280 }},
1282 }},
1288 }},
1291 }},
1295 }},
1297 }},
1298 /* if CPUID.0AH: EDX[4:0] > 0 */
1301 /* Also known as MSR_PERF_FIXED_CTR0 */
1303 }},
1304 /* if CPUID.0AH: EDX[4:0] > 1 */
1307 /* Also known as MSR_PERF_FIXED_CTR1 */
1309 }},
1310 /* if CPUID.0AH: EDX[4:0] > 2 */
1313 /* Also known as MSR_PERF_FIXED_CTR2 */
1315 }},
1316 /* if CPUID.01H: ECX[15] = 1 */
1318 /* Additional info available at Section 17.4.1 of
1319 * Intel 64 and IA-32 Architectures Software Developer's
1320 * Manual, Volume 3.
1321 */
1327 }},
1332 }},
1335 }},
1338 }},
1341 }},
1344 }},
1346 }},
1347 /* if CPUID.0AH: EAX[7:0] > 1*/
1350 /* Also known as MSR_PERF_FIXED_CTR_CTRL.
1351 * Counter increments while the results of ANDing respective enable bit
1352 * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits
1353 * in this MSR is true. */
1359 }},
1360 /* if CPUID.0AH EAX[7:0] > 2 */
1363 "conditions occurring in the logical processor "
1366 "occurring across all logical processors sharing "
1369 }},
1374 }},
1379 }},
1384 }},
1385 /* if CPUID.0AH: EAX[7:0] > 2 */
1388 "conditions occurring in the logical processor "
1391 "occurring across all logical processors sharing "
1394 }},
1399 }},
1404 }},
1409 }},
1410 /* if CPUID.0AH: EAX[7:0] > 2 */
1413 "conditions occurring in the logical processor "
1416 "occurring across all logical processors sharing "
1419 }},
1424 }},
1429 }},
1431 }},
1432 /* if CPUID.0AH: EAX[7:0] > 0 */
1435 /* Also known as MSR_PERF_GLOBAL_STATUS */
1436 /* if CPUID.0AH: EAX[7:0] > 0 */
1440 }},
1441 /* if CPUID.0AH: EAX[7:0] > 0 */
1445 }},
1446 /* if CPUID.0AH: EAX[7:0] > 2 */
1450 }},
1452 /* if CPUID.0AH: EAX[7:0] > 1 */
1456 }},
1457 /* if CPUID.0AH: EAX[7:0] > 1 */
1461 }},
1462 /* if CPUID.0AH: EAX[7:0] > 1 */
1466 }},
1468 /* presented only in 06_2EH Nehalem model */
1471 }},
1472 /* presented only in 06_2EH Nehalem model */
1475 }},
1476 /* if CPUID.0AH: EAX[7:0] > 0 */
1479 }},
1480 /* if CPUID.0AH: EAX[7:0] > 0 */
1483 }},
1485 }},
1486 /* if CPUID.0AH: EAX[7:0] > 0 */
1489 /* Counter increments while the result of ANDing respective
1490 * enable bit in this MSR with corresponding OS or USR bits
1491 * in general-purpose or fixed counter control MSR is true.
1492 */
1494 /* if CPUID.0AH: EAX[7:0] > 1 */
1497 }},
1498 /* if CPUID.0AH: EAX[7:0] > 1 */
1501 }},
1502 /* if CPUID.0AH: EAX[7:0] > 1 */
1505 }},
1507 /* if CPUID.0AH: EAX[7:0] > 0 */
1510 }},
1511 /* if CPUID.0AH: EAX[7:0] > 0 */
1514 }},
1516 }},
1517 /* if CPUID.0AH: EAX[7:0] > 0 */
1520 /* if CPUID.0AH: EAX[7:0] > 0 */
1523 }},
1524 /* if CPUID.0AH: EAX[7:0] > 0 */
1527 }},
1528 /* Presented only in 06_2EH Nehalem model */
1531 }},
1533 /* if CPUID.0AH: EAX[7:0] > 1 */
1536 }},
1537 /* if CPUID.0AH: EAX[7:0] > 1 */
1540 }},
1541 /* if CPUID.0AH: EAX[7:0] > 1 */
1544 }},
1546 /* if CPUID.0AH: EAX[7:0] > 0 */
1549 }},
1550 /* if CPUID.0AH: EAX[7:0] > 0 */
1553 }},
1555 }},
1556 /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures
1557 * Software Developer's Manual, Volume 3,
1558 * "Precise Event Based Sampling (PEBS)".
1559 */
1566 }},
1571 }},
1576 }},
1581 }},
1587 }},
1592 }},
1597 }},
1602 }},
1604 }},
1606 /* See Section 18.6.1.2 of Intel's manual
1607 * for additional information.
1608 */
1614 }},
1616 }},
1619 }},
1622 }},
1625 }},
1628 }},
1631 }},
1634 }},
1637 }},
1640 }},
1643 }},
1646 }},
1649 }},
1652 }},
1655 }},
1658 }},
1661 }},
1664 }},
1667 }},
1670 }},
1673 }},
1676 }},
1679 }},
1682 }},
1685 }},
1688 }},
1691 /* Additional info available at
1692 * Appendix A.1, "Basic VMX Information" */
1696 }},
1700 }},
1703 }},
1707 }},
1710 }},
1712 }},
1714 "Capability Reporting Register of "
1716 /* Additional info available at Appendix A.3,
1717 * "VM-Execution Controls" */
1719 }},
1721 "Capability Reporting Register of "
1723 /* Additional info available at Appendix A.3,
1724 * "VM-Execution Controls" */
1726 }},
1729 /* Additional info available at Appendix A.4,
1730 * "VM-Exit Controls" */
1732 }},
1735 /* Additional info available at Appendix A.5,
1736 * "VM-Entry Controls" */
1738 }},
1741 /* Additional info available at Appendix A.6,
1742 * "Miscellaneous Data" */
1744 }},
1747 /* Additional info available at Appendix A.7,
1748 * "VMX-Fixed Bits in CR0" */
1750 }},
1753 /* Additional info available at Appendix A.7,
1754 * "VMX-Fixed Bits in CR0" */
1756 }},
1759 /* Additional info available at Appendix A.8,
1760 * "VMX-Fixed Bits in CR4" */
1762 }},
1765 /* Additional info available at Appendix A.8,
1766 * "VMX-Fixed Bits in CR4" */
1768 }},
1771 /* Additional info available at Appendix A.9,
1772 * "VMCS Enumeration" */
1774 }},
1776 "Capability Reporting Register of Secondary "
1778 /* Additional info available at Appendix A.3,
1779 * "VM-Execution Controls" */
1781 }},
1782 /* Undocumented PECI control register */
1786 }},
1788 /* Additional info available at Section 18.10.4 of Intel 64
1789 * and IA-32 Architectures Software Developer's Manual,
1790 * "Debug Store (DS) Mechanism".
1791 */
1796 }},
1798 }},
1800 /* 16 registers - first
1801 * registers in sixteen pairs
1802 * of last branch record registers
1803 * on the last branch record stack
1804 */
1807 }},
1810 }},
1813 }},
1816 }},
1819 }},
1822 }},
1825 }},
1828 }},
1831 }},
1834 }},
1837 }},
1840 }},
1843 }},
1846 }},
1849 }},
1852 }},
1854 /* 16 registers - second
1855 * registers in sixteen pairs
1856 * of last branch record registers
1857 * on the last branch record stack
1858 */
1861 }},
1864 }},
1867 }},
1870 }},
1873 }},
1876 }},
1879 }},
1882 }},
1885 }},
1888 }},
1891 }},
1894 }},
1897 }},
1900 }},
1903 }},
1906 }},
1908 /* x2APIC registers - see Intel 64 Architecture x2APIC Specification */
1913 }},
1915 /* Same version between extended and legacy modes.
1916 * Bit 24 is available only to an x2APIC unit. */
1921 }},
1924 }},
1928 }},
1930 }},
1936 }},
1938 }},
1942 }},
1944 /* 0 is the only valid value to write. GP fault
1945 * on non-zero write. */
1948 }},
1950 /* Read Only in x2APIC mode, Read-Write in xAPIC mode. */
1953 }},
1959 }},
1965 }},
1968 }},
1970 }},
1974 }},
1978 }},
1982 }},
1986 }},
1990 }},
1994 }},
1998 }},
2002 }},
2006 }},
2010 }},
2014 }},
2018 }},
2022 }},
2026 }},
2030 }},
2034 }},
2038 }},
2042 }},
2046 }},
2050 }},
2054 }},
2058 }},
2062 }},
2066 }},
2068 /* GP fault on non-zero writes. */
2073 }},
2076 }},
2079 }},
2082 }},
2085 }},
2089 }},
2094 }},
2102 }},
2108 }},
2113 }},
2119 }},
2130 }},
2133 }},
2135 }},
2139 }},
2143 }},
2147 }},
2151 }},
2155 }},
2159 }},
2163 }},
2167 }},
2171 }},
2174 /* Only in x2APIC mode. */
2178 }},
2180 }},
2183 }},
2186 }},
2189 }},
2192 }},
2195 }},
2198 }},
2201 }},
2204 }},
2207 }},
2208 /* if CPUID.80000001H: EDX[29] = 1 or CPUID.80000001H: EDX[27] = 1 */
2216 }},
2221 }},
2224 /* Enable IA-32e Mode operation */
2226 }},
2229 /* Enable SYSCALL/SYSRET instructions
2230 * in 64-bit mode. */
2232 }},
2234 }},
2235 /* if CPUID.80000001H: EDX[29] = 1 */
2239 }},
2240 /* if CPUID.80000001H: EDX[29] = 1 */
2244 }},
2245 /* if CPUID.80000001H: EDX[29] = 1 */
2249 }},
2250 /* if CPUID.80000001H: EDX[29] = 1 */
2254 }},
2255 /* if CPUID.80000001H: EDX[29] = 1 */
2259 }},
2260 /* if CPUID.80000001H: EDX[29] = 1 */
2264 }},
2265 /* if CPUID.80000001H: EDX[27] = 1 */
2269 }},
2271 };