soc/amd/stoneyridge: remove LIDS field from global NVS
[coreboot.git] / payloads / libpayload / arch / arm / virtual.c
blob867a43b4426c56105c96781a5aab54265c0ff4a0
1 /*
3 * Copyright (C) 2008 coresystems GmbH
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
29 #include <libpayload.h>
30 #include <assert.h>
31 #include <die.h>
32 #include <stdlib.h>
33 #include <unistd.h>
34 #include <arch/cache.h>
35 #include <arch/virtual.h>
36 #include <arch/io.h>
38 unsigned long virtual_offset = 0;
39 extern char _end[];
42 * MAIR Index
43 * (Originally defined in src/arch/arm/include/armv7/arch/cache.h)
45 #define MAIR_INDX_NC 0
46 #define MAIR_INDX_WT 1
47 #define MAIR_INDX_WB 2
50 * Translation Table Attribute
51 * (Originally defined in src/arch/arm/include/armv7/arch/cache.h)
53 #define ATTR_BASE (\
54 0ULL << 54 | /* PN. 0:Not restricted */ \
55 0ULL << 53 | /* PXN. 0:Not restricted */ \
56 1 << 10 | /* AF. 1:Accessed. This is to prevent access \
57 * fault when accessed for the first time */ \
58 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
59 0 << 5 | /* NS. 0:Output address is in Secure space */ \
60 0 << 1 | /* block/table. 0:block entry */ \
61 1 << 0 /* validity. 1:valid */ \
63 #define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2))
64 #define ATTR_WT (ATTR_BASE | (MAIR_INDX_WT << 2))
65 #define ATTR_WB (ATTR_BASE | (MAIR_INDX_WB << 2))
67 /* Translation Table Entry */
68 typedef uint64_t pmd_t;
69 typedef uint64_t pgd_t;
71 #define SECTION_SHIFT 30
72 #define BLOCK_SHIFT 21
73 #define PAGE_SHIFT 12
74 #define PGD_MASK (~0 << PAGE_SHIFT)
76 static pmd_t *ttb_buff = 0;
77 static uintptr_t work_block;
78 static pmd_t original_map;
80 int getpagesize(void)
82 return 1 << PAGE_SHIFT;
85 static void lpae_map_init(void)
87 pgd_t *pgd;
89 die_if(!(read_ttbcr() >> 31), "LPAE is not enabled\n");
91 /* get work block address */
92 work_block = ALIGN_UP((uintptr_t)_end, 2*MiB);
93 assert(work_block);
94 printf("Work block for LPAE mapping is @ %p\n", (void *)work_block);
96 /* get the address of the 1st pmd from pgd[0] */
97 pgd = (pgd_t *)((uintptr_t)read_ttbr0() & PGD_MASK);
98 ttb_buff = (pmd_t *)((uintptr_t)pgd[0] & PGD_MASK);
99 assert(ttb_buff);
101 original_map = ttb_buff[work_block >> BLOCK_SHIFT];
104 static void lpae_flush_work_block(void)
106 dccmvac((uintptr_t)&ttb_buff[work_block >> BLOCK_SHIFT]);
107 dsb();
108 tlbimvaa(work_block);
109 dsb();
110 isb();
114 * Maps a 2MB designated block to a requested physical address, and returns
115 * the address to the block or NULL on error.
117 * pa_mb: Physical address in MB. Has to be on a 2MB boundary.
118 * policy: Data chache policy
120 void *lpae_map_phys_addr(unsigned long pa_mb, enum dcache_policy policy)
122 pmd_t attr;
124 if (!ttb_buff)
125 lpae_map_init();
127 switch(policy) {
128 case DCACHE_OFF:
129 attr = ATTR_NC;
130 break;
131 case DCACHE_WRITEBACK:
132 attr = ATTR_WB;
133 break;
134 case DCACHE_WRITETHROUGH:
135 attr = ATTR_WT;
136 break;
137 default:
138 return NULL;
141 ttb_buff[work_block >> BLOCK_SHIFT] =
142 ((pmd_t)pa_mb/2 << BLOCK_SHIFT) | attr;
144 lpae_flush_work_block();
146 return (void *)work_block;
149 void lpae_restore_map(void)
151 ttb_buff[work_block >> BLOCK_SHIFT] = original_map;
152 lpae_flush_work_block();