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soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
[coreboot.git] / src / commonlib / storage / sdhci.c
blob882920d6a40df93e715bff2ff28a2d1b0b4db5e2
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Secure Digital (SD) Host Controller interface specific code
4 */
5
6 #include "bouncebuf.h"
7 #include <commonlib/sd_mmc_ctrlr.h>
8 #include <commonlib/sdhci.h>
9 #include <commonlib/stdlib.h>
10 #include <commonlib/storage.h>
11 #include <delay.h>
12 #include <endian.h>
13 #include <lib.h>
14 #include "sdhci.h"
15 #include "sd_mmc.h"
16 #include "storage.h"
17 #include <timer.h>
18
19 #define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \
20 || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_SEPARATE_VERSTAGE) \
21 || (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_ROMSTAGE) \
22 || ENV_POSTCAR || ENV_RAMSTAGE)
23
24 __weak void *dma_malloc(size_t length_in_bytes)
25 {
26 return malloc(length_in_bytes);
27 }
28
29 void sdhci_reset(struct sdhci_ctrlr *sdhci_ctrlr, u8 mask)
30 {
31 struct stopwatch sw;
32
33 /* Wait max 100 ms */
34 stopwatch_init_msecs_expire(&sw, 100);
35
36 sdhci_writeb(sdhci_ctrlr, mask, SDHCI_SOFTWARE_RESET);
37 while (sdhci_readb(sdhci_ctrlr, SDHCI_SOFTWARE_RESET) & mask) {
38 if (stopwatch_expired(&sw)) {
39 sdhc_error("Reset 0x%x never completed.\n", (int)mask);
40 return;
41 }
42 udelay(1000);
43 }
44 }
45
46 void sdhci_cmd_done(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_command *cmd)
47 {
48 int i;
49 if (cmd->resp_type & CARD_RSP_136) {
50 /* CRC is stripped so we need to do some shifting. */
51 for (i = 0; i < 4; i++) {
52 cmd->response[i] = sdhci_readl(sdhci_ctrlr,
53 SDHCI_RESPONSE + (3-i)*4) << 8;
54 if (i != 3)
55 cmd->response[i] |= sdhci_readb(sdhci_ctrlr,
56 SDHCI_RESPONSE + (3-i)*4-1);
57 }
58 sdhc_log_response(4, &cmd->response[0]);
59 sdhc_trace("Response: 0x%08x.%08x.%08x.%08x\n",
60 cmd->response[3], cmd->response[2], cmd->response[1],
61 cmd->response[0]);
62 } else {
63 cmd->response[0] = sdhci_readl(sdhci_ctrlr, SDHCI_RESPONSE);
64 sdhc_log_response(1, &cmd->response[0]);
65 sdhc_trace("Response: 0x%08x\n", cmd->response[0]);
66 }
67 }
68
69 static int sdhci_transfer_data(struct sdhci_ctrlr *sdhci_ctrlr,
70 struct mmc_data *data, unsigned int start_addr)
71 {
72 uint32_t block_count;
73 uint32_t *buffer;
74 uint32_t *buffer_end;
75 uint32_t ps;
76 uint32_t ps_mask;
77 uint32_t stat;
78 struct stopwatch sw;
79
80 block_count = 0;
81 buffer = (uint32_t *)data->dest;
82 ps_mask = (data->flags & DATA_FLAG_READ)
83 ? SDHCI_DATA_AVAILABLE : SDHCI_SPACE_AVAILABLE;
84 stopwatch_init_msecs_expire(&sw, 100);
85 do {
86 /* Stop transfers if there is an error */
87 stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
88 sdhci_writel(sdhci_ctrlr, stat, SDHCI_INT_STATUS);
89 if (stat & SDHCI_INT_ERROR) {
90 sdhc_error("Error detected in status(0x%X)!\n", stat);
91 return -1;
92 }
93
94 /* Determine if the buffer is ready to move data */
95 ps = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
96 if (!(ps & ps_mask)) {
97 if (stopwatch_expired(&sw)) {
98 sdhc_error("Transfer data timeout\n");
99 return -1;
100 }
101 udelay(1);
102 continue;
103 }
104
105 /* Transfer a block of data */
106 buffer_end = &buffer[data->blocksize >> 2];
107 if (data->flags == DATA_FLAG_READ)
108 while (buffer_end > buffer)
109 *buffer++ = sdhci_readl(sdhci_ctrlr,
110 SDHCI_BUFFER);
111 else
112 while (buffer_end > buffer)
113 sdhci_writel(sdhci_ctrlr, *buffer++,
114 SDHCI_BUFFER);
115 if (++block_count >= data->blocks)
116 break;
117 } while (!(stat & SDHCI_INT_DATA_END));
118 return 0;
119 }
120
121 static int sdhci_send_command_bounced(struct sd_mmc_ctrlr *ctrlr,
122 struct mmc_command *cmd, struct mmc_data *data,
123 struct bounce_buffer *bbstate)
124 {
125 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
126 u16 mode = 0;
127 unsigned int stat = 0;
128 int ret = 0;
129 u32 mask, flags;
130 unsigned int timeout, start_addr = 0;
131 struct stopwatch sw;
132
133 /* Wait max 1 s */
134 timeout = 1000;
135
136 sdhci_writel(sdhci_ctrlr, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
137 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
138
139 /* We shouldn't wait for data inhibit for stop commands, even
140 though they might use busy signaling */
141 if (cmd->flags & CMD_FLAG_IGNORE_INHIBIT)
142 mask &= ~SDHCI_DATA_INHIBIT;
143
144 while (sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE) & mask) {
145 if (timeout == 0) {
146 sdhc_trace("Cmd: %2d, Arg: 0x%08x, not sent\n",
147 cmd->cmdidx, cmd->cmdarg);
148 sdhc_error("Controller never released inhibit bit(s), "
149 "present state %#8.8x.\n",
150 sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE));
151 return CARD_COMM_ERR;
152 }
153 timeout--;
154 udelay(1000);
155 }
156
157 mask = SDHCI_INT_RESPONSE;
158 if (!(cmd->resp_type & CARD_RSP_PRESENT))
159 flags = SDHCI_CMD_RESP_NONE;
160 else if (cmd->resp_type & CARD_RSP_136)
161 flags = SDHCI_CMD_RESP_LONG;
162 else if (cmd->resp_type & CARD_RSP_BUSY) {
163 flags = SDHCI_CMD_RESP_SHORT_BUSY;
164 mask |= SDHCI_INT_DATA_END;
165 } else
166 flags = SDHCI_CMD_RESP_SHORT;
167
168 if (cmd->resp_type & CARD_RSP_CRC)
169 flags |= SDHCI_CMD_CRC;
170 if (cmd->resp_type & CARD_RSP_OPCODE)
171 flags |= SDHCI_CMD_INDEX;
172 if (data)
173 flags |= SDHCI_CMD_DATA;
174
175 /* Set Transfer mode regarding to data flag */
176 if (data) {
177 sdhci_writew(sdhci_ctrlr,
178 SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
179 data->blocksize), SDHCI_BLOCK_SIZE);
180
181 if (data->flags == DATA_FLAG_READ)
182 mode |= SDHCI_TRNS_READ;
183
184 if (data->blocks > 1)
185 mode |= SDHCI_TRNS_BLK_CNT_EN |
186 SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
187
188 sdhci_writew(sdhci_ctrlr, data->blocks, SDHCI_BLOCK_COUNT);
189
190 if (DMA_AVAILABLE && (ctrlr->caps & DRVR_CAP_AUTO_CMD12)
191 && (cmd->cmdidx != MMC_CMD_AUTO_TUNING_SEQUENCE)) {
192 if (sdhci_setup_adma(sdhci_ctrlr, data))
193 return -1;
194 mode |= SDHCI_TRNS_DMA;
195 }
196 sdhci_writew(sdhci_ctrlr, mode, SDHCI_TRANSFER_MODE);
197 }
198
199 sdhc_trace("Cmd: %2d, Arg: 0x%08x\n", cmd->cmdidx, cmd->cmdarg);
200 sdhci_writel(sdhci_ctrlr, cmd->cmdarg, SDHCI_ARGUMENT);
201 sdhci_writew(sdhci_ctrlr, SDHCI_MAKE_CMD(cmd->cmdidx, flags),
202 SDHCI_COMMAND);
203 sdhc_log_command_issued();
204
205 if (DMA_AVAILABLE && (mode & SDHCI_TRNS_DMA))
206 return sdhci_complete_adma(sdhci_ctrlr, cmd);
207
208 stopwatch_init_msecs_expire(&sw, 2550);
209 do {
210 stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
211 if (stat & SDHCI_INT_ERROR) {
212 sdhc_trace("Error - IntStatus: 0x%08x\n", stat);
213 break;
214 }
215
216 if (stat & SDHCI_INT_DATA_AVAIL) {
217 sdhci_writel(sdhci_ctrlr, stat, SDHCI_INT_STATUS);
218 return 0;
219 }
220
221 /* Apply max timeout for R1b-type CMD defined in eMMC ext_csd
222 except for erase ones */
223 if (stopwatch_expired(&sw)) {
224 if (ctrlr->caps & DRVR_CAP_BROKEN_R1B)
225 return 0;
226 sdhc_error(
227 "Timeout for status update! IntStatus: 0x%08x\n",
228 stat);
229 return CARD_TIMEOUT;
230 }
231 } while ((stat & mask) != mask);
232
233 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
234 if (cmd->cmdidx)
235 sdhci_cmd_done(sdhci_ctrlr, cmd);
236 sdhci_writel(sdhci_ctrlr, mask, SDHCI_INT_STATUS);
237 } else
238 ret = -1;
239
240 if (!ret && data)
241 ret = sdhci_transfer_data(sdhci_ctrlr, data, start_addr);
242
243 if (ctrlr->udelay_wait_after_cmd)
244 udelay(ctrlr->udelay_wait_after_cmd);
245
246 stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
247 sdhci_writel(sdhci_ctrlr, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
248
249 if (!ret)
250 return 0;
251
252 sdhci_reset(sdhci_ctrlr, SDHCI_RESET_CMD);
253 sdhci_reset(sdhci_ctrlr, SDHCI_RESET_DATA);
254 if (stat & SDHCI_INT_TIMEOUT) {
255 sdhc_error("CMD%d timeout, IntStatus: 0x%08x\n", cmd->cmdidx,
256 stat);
257 return CARD_TIMEOUT;
258 }
259
260 sdhc_error("CMD%d failed, IntStatus: 0x%08x\n", cmd->cmdidx, stat);
261 return CARD_COMM_ERR;
262 }
263
264 __weak void sdhc_log_command(struct mmc_command *cmd)
265 {
266 }
267
268 __weak void sdhc_log_command_issued(void)
269 {
270 }
271
272 __weak void sdhc_log_response(uint32_t entries,
273 uint32_t *response)
274 {
275 }
276
277 __weak void sdhc_log_ret(int ret)
278 {
279 }
280
281 static void sdhci_led_control(struct sd_mmc_ctrlr *ctrlr, int on)
282 {
283 uint8_t host_ctrl;
284 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
285
286 host_ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_HOST_CONTROL);
287 host_ctrl &= ~SDHCI_CTRL_LED;
288 if (on)
289 host_ctrl |= SDHCI_CTRL_LED;
290 sdhci_writeb(sdhci_ctrlr, host_ctrl, SDHCI_HOST_CONTROL);
291 }
292
293 static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr,
294 struct mmc_command *cmd, struct mmc_data *data)
295 {
296 void *buf;
297 unsigned int bbflags;
298 size_t len;
299 struct bounce_buffer *bbstate = NULL;
300 struct bounce_buffer bbstate_val;
301 int ret;
302
303 sdhc_log_command(cmd);
304
305 if (CONFIG(SDHCI_BOUNCE_BUFFER) && data) {
306 if (data->flags & DATA_FLAG_READ) {
307 buf = data->dest;
308 bbflags = GEN_BB_WRITE;
309 } else {
310 buf = (void *)data->src;
311 bbflags = GEN_BB_READ;
312 }
313 len = data->blocks * data->blocksize;
314
315 /*
316 * on some platform(like rk3399 etc) need to worry about
317 * cache coherency, so check the buffer, if not dma
318 * coherent, use bounce_buffer to do DMA management.
319 */
320 if (!dma_coherent(buf)) {
321 bbstate = &bbstate_val;
322 if (bounce_buffer_start(bbstate, buf, len, bbflags)) {
323 sdhc_error("Failed to get bounce buffer.\n");
324 return -1;
325 }
326 }
327 }
328
329 sdhci_led_control(ctrlr, 1);
330 ret = sdhci_send_command_bounced(ctrlr, cmd, data, bbstate);
331 sdhci_led_control(ctrlr, 0);
332 sdhc_log_ret(ret);
333
334 if (CONFIG(SDHCI_BOUNCE_BUFFER) && bbstate)
335 bounce_buffer_stop(bbstate);
336
337 return ret;
338 }
339
340 static int sdhci_set_clock(struct sdhci_ctrlr *sdhci_ctrlr, unsigned int clock)
341 {
342 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
343 unsigned int actual, div, clk, timeout;
344
345 /* Turn off the clock if requested */
346 actual = clock;
347 if (actual == 0) {
348 sdhci_writew(sdhci_ctrlr, 0, SDHCI_CLOCK_CONTROL);
349 sdhc_debug("SDHCI bus clock: Off\n");
350 return 0;
351 }
352
353 /* Compute the divisor for the new clock frequency */
354 actual = MIN(actual, ctrlr->f_max);
355 actual = MAX(actual, ctrlr->f_min);
356 if (ctrlr->clock_base <= actual)
357 div = 0;
358 else {
359 /* Version 3.00 divisors must be a multiple of 2. */
360 if ((ctrlr->version & SDHCI_SPEC_VER_MASK)
361 >= SDHCI_SPEC_300) {
362 div = MIN(((ctrlr->clock_base + actual - 1)
363 / actual), SDHCI_MAX_DIV_SPEC_300);
364 actual = ctrlr->clock_base / div;
365 div += 1;
366 } else {
367 /* Version 2.00 divisors must be a power of 2. */
368 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
369 if ((ctrlr->clock_base / div) <= actual)
370 break;
371 }
372 actual = ctrlr->clock_base / div;
373 }
374 div >>= 1;
375 }
376
377 /* Set the new clock frequency */
378 if (actual != ctrlr->bus_hz) {
379 /* Turn off the clock */
380 sdhci_writew(sdhci_ctrlr, 0, SDHCI_CLOCK_CONTROL);
381
382 /* Set the new clock frequency */
383 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
384 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
385 << SDHCI_DIVIDER_HI_SHIFT;
386 clk |= SDHCI_CLOCK_INT_EN;
387 sdhci_writew(sdhci_ctrlr, clk, SDHCI_CLOCK_CONTROL);
388
389 /* Display the requested clock frequency */
390 sdhc_debug("SDHCI bus clock: %d.%03d MHz\n",
391 actual / 1000000,
392 (actual / 1000) % 1000);
393
394 /* Wait max 20 ms */
395 timeout = 20;
396 while (!((clk = sdhci_readw(sdhci_ctrlr, SDHCI_CLOCK_CONTROL))
397 & SDHCI_CLOCK_INT_STABLE)) {
398 if (timeout == 0) {
399 sdhc_error(
400 "Internal clock never stabilised.\n");
401 return -1;
402 }
403 timeout--;
404 udelay(1000);
405 }
406
407 clk |= SDHCI_CLOCK_CARD_EN;
408 sdhci_writew(sdhci_ctrlr, clk, SDHCI_CLOCK_CONTROL);
409 ctrlr->bus_hz = actual;
410 }
411 return 0;
412 }
413
414 static void sdhci_set_power(struct sdhci_ctrlr *sdhci_ctrlr,
415 unsigned short power)
416 {
417 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
418 u8 pwr = 0;
419 u8 pwr_ctrl;
420 const char *voltage;
421
422 if (power != (unsigned short)-1) {
423 switch (1 << power) {
424 case MMC_VDD_165_195:
425 voltage = "1.8";
426 pwr = SDHCI_POWER_180;
427 break;
428 case MMC_VDD_29_30:
429 case MMC_VDD_30_31:
430 voltage = "3.0";
431 pwr = SDHCI_POWER_300;
432 break;
433 case MMC_VDD_32_33:
434 case MMC_VDD_33_34:
435 voltage = "3.3";
436 pwr = SDHCI_POWER_330;
437 break;
438 }
439 }
440
441 /* Determine the power state */
442 pwr_ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_POWER_CONTROL);
443 if (pwr == 0) {
444 if (pwr_ctrl & SDHCI_POWER_ON)
445 sdhc_debug("SDHCI voltage: Off\n");
446 sdhci_writeb(sdhci_ctrlr, 0, SDHCI_POWER_CONTROL);
447 return;
448 }
449
450 /* Determine if the power has changed */
451 if (pwr_ctrl != (pwr | SDHCI_POWER_ON)) {
452 sdhc_debug("SDHCI voltage: %s Volts\n", voltage);
453
454 /* Select the voltage */
455 if (ctrlr->caps & DRVR_CAP_NO_SIMULT_VDD_AND_POWER)
456 sdhci_writeb(sdhci_ctrlr, pwr, SDHCI_POWER_CONTROL);
457
458 /* Apply power to the SD/MMC device */
459 pwr |= SDHCI_POWER_ON;
460 sdhci_writeb(sdhci_ctrlr, pwr, SDHCI_POWER_CONTROL);
461 }
462 }
463
464 const u16 speed_driver_voltage[] = {
465 0, /* 0: BUS_TIMING_LEGACY */
466 0, /* 1: BUS_TIMING_MMC_HS */
467 0, /* 2: BUS_TIMING_SD_HS */
468 SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180, /* 3: BUS_TIMING_UHS_SDR12 */
469 SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180, /* 4: BUS_TIMING_UHS_SDR25 */
470 SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180, /* 5: BUS_TIMING_UHS_SDR50 */
471 /* 6: BUS_TIMING_UHS_SDR104 */
472 SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
473 SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180, /* 7: BUS_TIMING_UHS_DDR50 */
474 SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180, /* 8: BUS_TIMING_MMC_DDR52 */
475 /* 9: BUS_TIMING_MMC_HS200 */
476 SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
477 /* 10: BUS_TIMING_MMC_HS400 */
478 SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
479 /* 11: BUS_TIMING_MMC_HS400ES */
480 SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180
481 };
482
483 static void sdhci_set_uhs_signaling(struct sdhci_ctrlr *sdhci_ctrlr,
484 uint32_t timing)
485 {
486 u16 ctrl_2;
487
488 /* Select bus speed mode, driver and VDD 1.8 volt support */
489 ctrl_2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
490 ctrl_2 &= ~(SDHCI_CTRL_UHS_MASK | SDHCI_CTRL_DRV_TYPE_MASK
491 | SDHCI_CTRL_VDD_180);
492 if (timing < ARRAY_SIZE(speed_driver_voltage))
493 ctrl_2 |= speed_driver_voltage[timing];
494 sdhci_writew(sdhci_ctrlr, ctrl_2, SDHCI_HOST_CONTROL2);
495 }
496
497 static void sdhci_set_ios(struct sd_mmc_ctrlr *ctrlr)
498 {
499 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
500 u32 ctrl;
501 u32 previous_ctrl;
502 u32 bus_width;
503 int version;
504
505 /* Set the clock frequency */
506 if (ctrlr->bus_hz != ctrlr->request_hz)
507 sdhci_set_clock(sdhci_ctrlr, ctrlr->request_hz);
508
509 /* Switch to 1.8 volt for HS200 */
510 if (ctrlr->caps & DRVR_CAP_1V8_VDD)
511 if (ctrlr->bus_hz == CLOCK_200MHZ)
512 sdhci_set_power(sdhci_ctrlr, MMC_VDD_165_195_SHIFT);
513
514 /* Determine the new bus width */
515 bus_width = 1;
516 ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_HOST_CONTROL);
517 previous_ctrl = ctrl;
518 ctrl &= ~SDHCI_CTRL_4BITBUS;
519 version = ctrlr->version & SDHCI_SPEC_VER_MASK;
520 if (version >= SDHCI_SPEC_300)
521 ctrl &= ~SDHCI_CTRL_8BITBUS;
522
523 if ((ctrlr->bus_width == 8) && (version >= SDHCI_SPEC_300)) {
524 ctrl |= SDHCI_CTRL_8BITBUS;
525 bus_width = 8;
526 } else if (ctrlr->bus_width == 4) {
527 ctrl |= SDHCI_CTRL_4BITBUS;
528 bus_width = 4;
529 }
530
531 if (!(ctrlr->timing == BUS_TIMING_LEGACY) &&
532 !(ctrlr->caps & DRVR_CAP_NO_HISPD_BIT))
533 ctrl |= SDHCI_CTRL_HISPD;
534 else
535 ctrl &= ~SDHCI_CTRL_HISPD;
536
537 sdhci_set_uhs_signaling(sdhci_ctrlr, ctrlr->timing);
538
539 if (DMA_AVAILABLE) {
540 if (ctrlr->caps & DRVR_CAP_AUTO_CMD12) {
541 ctrl &= ~SDHCI_CTRL_DMA_MASK;
542 if (ctrlr->caps & DRVR_CAP_DMA_64BIT)
543 ctrl |= SDHCI_CTRL_ADMA64;
544 else
545 ctrl |= SDHCI_CTRL_ADMA32;
546 }
547 }
548
549 /* Set the new bus width */
550 if (CONFIG(SDHC_DEBUG)
551 && ((ctrl ^ previous_ctrl) & (SDHCI_CTRL_4BITBUS
552 | ((version >= SDHCI_SPEC_300) ? SDHCI_CTRL_8BITBUS : 0))))
553 sdhc_debug("SDHCI bus width: %d bit%s\n", bus_width,
554 (bus_width != 1) ? "s" : "");
555 sdhci_writeb(sdhci_ctrlr, ctrl, SDHCI_HOST_CONTROL);
556 }
557
558 static void sdhci_tuning_start(struct sd_mmc_ctrlr *ctrlr, int retune)
559 {
560 uint16_t host_ctrl2;
561 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
562
563 /* Start the bus tuning */
564 host_ctrl2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
565 host_ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
566 host_ctrl2 |= (retune ? SDHCI_CTRL_TUNED_CLK : 0)
567 | SDHCI_CTRL_EXEC_TUNING;
568 sdhci_writew(sdhci_ctrlr, host_ctrl2, SDHCI_HOST_CONTROL2);
569 }
570
571 static int sdhci_is_tuning_complete(struct sd_mmc_ctrlr *ctrlr, int *successful)
572 {
573 uint16_t host_ctrl2;
574 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
575
576 /* Determine if the bus tuning has completed */
577 host_ctrl2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
578 *successful = ((host_ctrl2 & SDHCI_CTRL_TUNED_CLK) != 0);
579 return ((host_ctrl2 & SDHCI_CTRL_EXEC_TUNING) == 0);
580 }
581
582 /* Prepare SDHCI controller to be initialized */
583 static int sdhci_pre_init(struct sdhci_ctrlr *sdhci_ctrlr)
584 {
585 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
586 unsigned int caps, caps_1;
587
588 /*
589 * If the device needs to do anything non-standard before
590 * sdhci initialization, run it here.
591 */
592 if (sdhci_ctrlr->attach) {
593 int rv = sdhci_ctrlr->attach(sdhci_ctrlr);
594 if (rv)
595 return rv;
596 }
597
598 /* Get controller version and capabilities */
599 ctrlr->version = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_VERSION) & 0xff;
600 caps = sdhci_readl(sdhci_ctrlr, SDHCI_CAPABILITIES);
601 caps_1 = sdhci_readl(sdhci_ctrlr, SDHCI_CAPABILITIES_1);
602
603 /* Determine the supported voltages */
604 if (caps & SDHCI_CAN_VDD_330)
605 ctrlr->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
606 if (caps & SDHCI_CAN_VDD_300)
607 ctrlr->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
608 if (caps & SDHCI_CAN_VDD_180)
609 ctrlr->voltages |= MMC_VDD_165_195;
610
611 /* Get the controller's base clock frequency */
612 if ((ctrlr->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
613 ctrlr->clock_base = (caps & SDHCI_CLOCK_V3_BASE_MASK)
614 >> SDHCI_CLOCK_BASE_SHIFT;
615 else
616 ctrlr->clock_base = (caps & SDHCI_CLOCK_BASE_MASK)
617 >> SDHCI_CLOCK_BASE_SHIFT;
618 ctrlr->clock_base *= 1000000;
619 ctrlr->f_max = ctrlr->clock_base;
620
621 /* Determine the controller's clock frequency range */
622 ctrlr->f_min = 0;
623 if ((ctrlr->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
624 ctrlr->f_min =
625 ctrlr->clock_base / SDHCI_MAX_DIV_SPEC_300;
626 else
627 ctrlr->f_min =
628 ctrlr->clock_base / SDHCI_MAX_DIV_SPEC_200;
629
630 /* Determine the controller's modes of operation */
631 ctrlr->caps |= DRVR_CAP_HS52 | DRVR_CAP_HS;
632 if (ctrlr->clock_base >= CLOCK_200MHZ) {
633 ctrlr->caps |= DRVR_CAP_HS200 | DRVR_CAP_HS200_TUNING;
634 if (caps_1 & SDHCI_SUPPORT_HS400)
635 ctrlr->caps |= DRVR_CAP_HS400
636 | DRVR_CAP_ENHANCED_STROBE;
637 }
638
639 /* Determine the bus widths the controller supports */
640 ctrlr->caps |= DRVR_CAP_4BIT;
641 if (caps & SDHCI_CAN_DO_8BIT)
642 ctrlr->caps |= DRVR_CAP_8BIT;
643
644 /* Determine the controller's DMA support */
645 if (caps & SDHCI_CAN_DO_ADMA2)
646 ctrlr->caps |= DRVR_CAP_AUTO_CMD12;
647 if (DMA_AVAILABLE && (caps & SDHCI_CAN_64BIT))
648 ctrlr->caps |= DRVR_CAP_DMA_64BIT;
649
650 /* Specify the modes that the driver stack supports */
651 ctrlr->caps |= DRVR_CAP_HC;
652
653 /* Let the SOC adjust the configuration to handle controller quirks */
654 soc_sd_mmc_controller_quirks(&sdhci_ctrlr->sd_mmc_ctrlr);
655 if (ctrlr->clock_base == 0) {
656 sdhc_error("Hardware doesn't specify base clock frequency\n");
657 return -1;
658 }
659 if (!ctrlr->f_max)
660 ctrlr->f_max = ctrlr->clock_base;
661
662 /* Display the results */
663 sdhc_trace("0x%08x: ctrlr->caps\n", ctrlr->caps);
664 sdhc_trace("%d.%03d MHz: ctrlr->clock_base\n",
665 ctrlr->clock_base / 1000000,
666 (ctrlr->clock_base / 1000) % 1000);
667 sdhc_trace("%d.%03d MHz: ctrlr->f_max\n",
668 ctrlr->f_max / 1000000,
669 (ctrlr->f_max / 1000) % 1000);
670 sdhc_trace("%d.%03d MHz: ctrlr->f_min\n",
671 ctrlr->f_min / 1000000,
672 (ctrlr->f_min / 1000) % 1000);
673 sdhc_trace("0x%08x: ctrlr->voltages\n", ctrlr->voltages);
674
675 sdhci_reset(sdhci_ctrlr, SDHCI_RESET_ALL);
676
677 return 0;
678 }
679
680 __weak void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr
681 *ctrlr)
682 {
683 }
684
685 static int sdhci_init(struct sdhci_ctrlr *sdhci_ctrlr)
686 {
687 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
688 int rv;
689
690 /* Only initialize the controller upon reset or card insertion */
691 if (ctrlr->initialized)
692 return 0;
693
694 sdhc_debug("SDHCI Controller Base Address: %p\n",
695 sdhci_ctrlr->ioaddr);
696
697 rv = sdhci_pre_init(sdhci_ctrlr);
698 if (rv)
699 return rv; /* The error has been already reported */
700
701 sdhci_set_power(sdhci_ctrlr, __fls(ctrlr->voltages));
702
703 if (ctrlr->caps & DRVR_CAP_NO_CD) {
704 unsigned int status;
705
706 sdhci_writel(sdhci_ctrlr, SDHCI_CTRL_CD_TEST_INS
707 | SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
708
709 status = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
710 while ((!(status & SDHCI_CARD_PRESENT)) ||
711 (!(status & SDHCI_CARD_STATE_STABLE)) ||
712 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
713 status = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
714 }
715
716 /* Enable only interrupts served by the SD controller */
717 sdhci_writel(sdhci_ctrlr, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
718 SDHCI_INT_ENABLE);
719 /* Mask all sdhci interrupt sources */
720 sdhci_writel(sdhci_ctrlr, 0x0, SDHCI_SIGNAL_ENABLE);
721
722 /* Set timeout to maximum, shouldn't happen if everything's right. */
723 sdhci_writeb(sdhci_ctrlr, 0xe, SDHCI_TIMEOUT_CONTROL);
724
725 mdelay(10);
726 ctrlr->initialized = 1;
727 return 0;
728 }
729
730 static int sdhci_update(struct sdhci_ctrlr *sdhci_ctrlr)
731 {
732 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
733
734 if (ctrlr->caps & DRVR_CAP_REMOVABLE) {
735 int present = (sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE) &
736 SDHCI_CARD_PRESENT) != 0;
737
738 if (!present) {
739 /* A card was present indicate the controller needs
740 * initialization on the next call.
741 */
742 ctrlr->initialized = 0;
743 return 0;
744 }
745 }
746
747 /* A card is present, get it ready. */
748 if (sdhci_init(sdhci_ctrlr))
749 return -1;
750 return 0;
751 }
752
753 void sdhci_update_pointers(struct sdhci_ctrlr *sdhci_ctrlr)
754 {
755 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
756
757 /* Update the routine pointers */
758 ctrlr->send_cmd = &sdhci_send_command;
759 ctrlr->set_ios = &sdhci_set_ios;
760 ctrlr->tuning_start = &sdhci_tuning_start;
761 ctrlr->is_tuning_complete = &sdhci_is_tuning_complete;
762 }
763
764 int add_sdhci(struct sdhci_ctrlr *sdhci_ctrlr)
765 {
766 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
767
768 sdhci_update_pointers(sdhci_ctrlr);
769
770 /* TODO(vbendeb): check if SDHCI spec allows to retrieve this value. */
771 ctrlr->b_max = 65535;
772
773 /* Initialize the SDHC controller */
774 return sdhci_update(sdhci_ctrlr);
775 }
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