src/device/dram/ddr3.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /**
   4  * @file ddr3.c
   5  *
   6  * \brief Utilities for decoding DDR3 SPDs
   7  */
   8
   9 #include <console/console.h>
  10 #include <device/device.h>
  11 #include <device/dram/ddr3.h>
  12 #include <device/dram/common.h>
  13 #include <string.h>
  14 #include <memory_info.h>
  15 #include <cbmem.h>
  16 #include <smbios.h>
  17 #include <types.h>
  18
  19 /*==============================================================================
  20  * = DDR3 SPD decoding helpers
  21  *----------------------------------------------------------------------------*/
  22
  23 /**
  24  * \brief Checks if the DIMM is Registered based on byte[3] of the SPD
  25  *
  26  * Tells if the DIMM type is registered or not.
  27  *
  28  * @param type DIMM type. This is byte[3] of the SPD.
  29  */
  30 int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type)
  31 {
  32         if ((type == SPD_DDR3_DIMM_TYPE_RDIMM) | (type == SPD_DDR3_DIMM_TYPE_MINI_RDIMM) |
  33                         (type == SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM))
  34                 return 1;
  35
  36         return 0;
  37 }
  38
  39 /**
  40  * \brief Calculate the CRC of a DDR3 SPD
  41  *
  42  * @param spd pointer to raw SPD data
  43  * @param len length of data in SPD
  44  *
  45  * @return the CRC of the SPD data, or 0 when spd data is truncated.
  46  */
  47 u16 spd_ddr3_calc_crc(u8 *spd, int len)
  48 {
  49         int n_crc;
  50
  51         /* Find the number of bytes covered by CRC */
  52         if (spd[0] & 0x80) {
  53                 n_crc = 117;
  54         } else {
  55                 n_crc = 126;
  56         }
  57
  58         if (len < n_crc)
  59                 /* Not enough bytes available to get the CRC */
  60                 return 0;
  61
  62         return ddr_crc16(spd, n_crc);
  63 }
  64
  65 /**
  66  * \brief Calculate the CRC of a DDR3 SPD unique identifier
  67  *
  68  * @param spd pointer to raw SPD data
  69  * @param len length of data in SPD
  70  *
  71  * @return the CRC of SPD data bytes 117..127, or 0 when spd data is truncated.
  72  */
  73 u16 spd_ddr3_calc_unique_crc(u8 *spd, int len)
  74 {
  75         if (len < (117 + 11))
  76                 /* Not enough bytes available to get the CRC */
  77                 return 0;
  78
  79         return ddr_crc16(&spd[117], 11);
  80 }
  81
  82 /**
  83  * \brief Decode the raw SPD data
  84  *
  85  * Decodes a raw SPD data from a DDR3 DIMM, and organizes it into a
  86  * @ref dimm_attr structure. The SPD data must first be read in a contiguous
  87  * array, and passed to this function.
  88  *
  89  * @param dimm pointer to @ref dimm_attr structure where the decoded data is to
  90  *             be stored
  91  * @param spd array of raw data previously read from the SPD.
  92  *
  93  * @return @ref spd_status enumerator
  94  *              SPD_STATUS_OK -- decoding was successful
  95  *              SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD
  96  *              SPD_STATUS_CRC_ERROR -- CRC did not verify
  97  *              SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
  98  *                                          detected.
  99  */
 100 int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
 101 {
 102         int ret;
 103         u16 crc, spd_crc;
 104         u8 capacity_shift, bus_width;
 105         u8 reg8;
 106         u32 mtb; /* medium time base */
 107         u32 ftb; /* fine time base */
 108         unsigned int val;
 109
 110         ret = SPD_STATUS_OK;
 111
 112         /* Don't assume we memset 0 dimm struct. Clear all our flags */
 113         dimm->flags.raw = 0;
 114         dimm->dimms_per_channel = 3;
 115
 116         /* Make sure that the SPD dump is indeed from a DDR3 module */
 117         if (spd[2] != SPD_MEMORY_TYPE_SDRAM_DDR3) {
 118                 printram("Not a DDR3 SPD!\n");
 119                 dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 120                 return SPD_STATUS_INVALID;
 121         }
 122         dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3;
 123         dimm->dimm_type = spd[3] & 0xf;
 124
 125         crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data));
 126         /* Compare with the CRC in the SPD */
 127         spd_crc = (spd[127] << 8) + spd[126];
 128         /* Verify the CRC is correct */
 129         if (crc != spd_crc) {
 130                 printram("ERROR: SPD CRC failed!!!\n");
 131                 ret = SPD_STATUS_CRC_ERROR;
 132         };
 133
 134         printram("  Revision           : %x\n", spd[1]);
 135         printram("  Type               : %x\n", spd[2]);
 136         printram("  Key                : %x\n", spd[3]);
 137
 138         reg8 = spd[4];
 139         /* Number of memory banks */
 140         val = (reg8 >> 4) & 0x07;
 141         if (val > 0x03) {
 142                 printram("  Invalid number of memory banks\n");
 143                 ret = SPD_STATUS_INVALID_FIELD;
 144         }
 145         printram("  Banks              : %u\n", 1 << (val + 3));
 146         /* SDRAM capacity */
 147         capacity_shift = reg8 & 0x0f;
 148         if (capacity_shift > 0x06) {
 149                 printram("  Invalid module capacity\n");
 150                 ret = SPD_STATUS_INVALID_FIELD;
 151         }
 152         if (capacity_shift < 0x02) {
 153                 printram("  Capacity           : %u Mb\n", 256 << capacity_shift);
 154         } else {
 155                 printram("  Capacity           : %u Gb\n", 1 << (capacity_shift - 2));
 156         }
 157
 158         reg8 = spd[5];
 159         /* Row address bits */
 160         val = (reg8 >> 3) & 0x07;
 161         if (val > 0x04) {
 162                 printram("  Invalid row address bits\n");
 163                 ret = SPD_STATUS_INVALID_FIELD;
 164         }
 165         dimm->row_bits = val + 12;
 166         /* Column address bits */
 167         val = reg8 & 0x07;
 168         if (val > 0x03) {
 169                 printram("  Invalid column address bits\n");
 170                 ret = SPD_STATUS_INVALID_FIELD;
 171         }
 172         dimm->col_bits = val + 9;
 173
 174         /* Module nominal voltage */
 175         reg8 = spd[6];
 176         printram("  Supported voltages :");
 177         if (reg8 & (1 << 2)) {
 178                 dimm->flags.operable_1_25V = 1;
 179                 dimm->voltage = 1250;
 180                 printram(" 1.25V");
 181         }
 182         if (reg8 & (1 << 1)) {
 183                 dimm->flags.operable_1_35V = 1;
 184                 dimm->voltage = 1300;
 185                 printram(" 1.35V");
 186         }
 187         if (!(reg8 & (1 << 0))) {
 188                 dimm->flags.operable_1_50V = 1;
 189                 dimm->voltage = 1500;
 190                 printram(" 1.5V");
 191         }
 192         printram("\n");
 193
 194         /* Module organization */
 195         reg8 = spd[7];
 196         /* Number of ranks */
 197         val = (reg8 >> 3) & 0x07;
 198         if (val > 3) {
 199                 printram("  Invalid number of ranks\n");
 200                 ret = SPD_STATUS_INVALID_FIELD;
 201         }
 202         dimm->ranks = val + 1;
 203         /* SDRAM device width */
 204         val = (reg8 & 0x07);
 205         if (val > 3) {
 206                 printram("  Invalid SDRAM width\n");
 207                 ret = SPD_STATUS_INVALID_FIELD;
 208         }
 209         dimm->width = (4 << val);
 210         printram("  SDRAM width        : %u\n", dimm->width);
 211
 212         /* Memory bus width */
 213         reg8 = spd[8];
 214         /* Bus extension */
 215         val = (reg8 >> 3) & 0x03;
 216         if (val > 1) {
 217                 printram("  Invalid bus extension\n");
 218                 ret = SPD_STATUS_INVALID_FIELD;
 219         }
 220         dimm->flags.is_ecc = val ? 1 : 0;
 221         printram("  Bus extension      : %u bits\n", val ? 8 : 0);
 222         /* Bus width */
 223         val = reg8 & 0x07;
 224         if (val > 3) {
 225                 printram("  Invalid bus width\n");
 226                 ret = SPD_STATUS_INVALID_FIELD;
 227         }
 228         bus_width = 8 << val;
 229         printram("  Bus width          : %u\n", bus_width);
 230
 231         /* We have all the info we need to compute the dimm size */
 232         /* Capacity is 256Mbit multiplied by the power of 2 specified in
 233          * capacity_shift
 234          * The rest is the JEDEC formula */
 235         dimm->size_mb =
 236                 ((1 << (capacity_shift + (25 - 20))) * bus_width * dimm->ranks) / dimm->width;
 237
 238         /* Medium Timebase =
 239          *   Medium Timebase (MTB) Dividend /
 240          *   Medium Timebase (MTB) Divisor */
 241         mtb = (((u32)spd[10]) << 8) / spd[11];
 242
 243         /* SDRAM Minimum Cycle Time (tCKmin) */
 244         dimm->tCK = spd[12] * mtb;
 245         /* CAS Latencies Supported */
 246         dimm->cas_supported = (spd[15] << 8) + spd[14];
 247         /* Minimum CAS Latency Time (tAAmin) */
 248         dimm->tAA = spd[16] * mtb;
 249         /* Minimum Write Recovery Time (tWRmin) */
 250         dimm->tWR = spd[17] * mtb;
 251         /* Minimum RAS# to CAS# Delay Time (tRCDmin) */
 252         dimm->tRCD = spd[18] * mtb;
 253         /* Minimum Row Active to Row Active Delay Time (tRRDmin) */
 254         dimm->tRRD = spd[19] * mtb;
 255         /* Minimum Row Precharge Delay Time (tRPmin) */
 256         dimm->tRP = spd[20] * mtb;
 257         /* Minimum Active to Precharge Delay Time (tRASmin) */
 258         dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb;
 259         /* Minimum Active to Active/Refresh Delay Time (tRCmin) */
 260         dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb;
 261         /* Minimum Refresh Recovery Delay Time (tRFCmin) */
 262         dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb;
 263         /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */
 264         dimm->tWTR = spd[26] * mtb;
 265         /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */
 266         dimm->tRTP = spd[27] * mtb;
 267         /* Minimum Four Activate Window Delay Time (tFAWmin) */
 268         dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb;
 269         /* Minimum CAS Write Latency Time (tCWLmin)
 270          * - not present in standard SPD */
 271         dimm->tCWL = 0;
 272         /* System CMD Rate Mode - not present in standard SPD */
 273         dimm->tCMD = 0;
 274
 275         printram("  FTB timings        :");
 276         /* FTB is introduced in SPD revision 1.1 */
 277         if (spd[1] >= 0x11 && spd[9] & 0x0f) {
 278                 printram(" yes\n");
 279
 280                 /* Fine timebase (1/256 ps) =
 281                  *   Fine Timebase (FTB) Dividend /
 282                  *   Fine Timebase (FTB) Divisor */
 283                 ftb = (((u16)spd[9] & 0xf0) << 4) / (spd[9] & 0x0f);
 284
 285                 /* SPD recommends to round up the MTB part and use a negative
 286                  * FTB, so a negative rounding should be always safe */
 287
 288                 /* SDRAM Minimum Cycle Time (tCKmin) correction */
 289                 dimm->tCK += (s32)((s8)spd[34] * ftb - 500) / 1000;
 290                 /* Minimum CAS Latency Time (tAAmin) correction */
 291                 dimm->tAA += (s32)((s8)spd[35] * ftb - 500) / 1000;
 292                 /* Minimum RAS# to CAS# Delay Time (tRCDmin) correction */
 293                 dimm->tRCD += (s32)((s8)spd[36] * ftb - 500) / 1000;
 294                 /* Minimum Row Precharge Delay Time (tRPmin) correction */
 295                 dimm->tRP += (s32)((s8)spd[37] * ftb - 500) / 1000;
 296                 /* Minimum Active to Active/Refresh Delay Time (tRCmin) corr. */
 297                 dimm->tRC += (s32)((s8)spd[38] * ftb - 500) / 1000;
 298         } else {
 299                 printram(" no\n");
 300         }
 301
 302         /* SDRAM Optional Features */
 303         reg8 = spd[30];
 304         printram("  Optional features  :");
 305         if (reg8 & 0x80) {
 306                 dimm->flags.dll_off_mode = 1;
 307                 printram(" DLL-Off_mode");
 308         }
 309         if (reg8 & 0x02) {
 310                 dimm->flags.rzq7_supported = 1;
 311                 printram(" RZQ/7");
 312         }
 313         if (reg8 & 0x01) {
 314                 dimm->flags.rzq6_supported = 1;
 315                 printram(" RZQ/6");
 316         }
 317         printram("\n");
 318
 319         /* SDRAM Thermal and Refresh Options */
 320         reg8 = spd[31];
 321         printram("  Thermal features   :");
 322         if (reg8 & 0x80) {
 323                 dimm->flags.pasr = 1;
 324                 printram(" PASR");
 325         }
 326         if (reg8 & 0x08) {
 327                 dimm->flags.odts = 1;
 328                 printram(" ODTS");
 329         }
 330         if (reg8 & 0x04) {
 331                 dimm->flags.asr = 1;
 332                 printram(" ASR");
 333         }
 334         if (reg8 & 0x02) {
 335                 dimm->flags.ext_temp_range = 1;
 336                 printram(" ext_temp_refresh");
 337         }
 338         if (reg8 & 0x01) {
 339                 dimm->flags.ext_temp_refresh = 1;
 340                 printram(" ext_temp_range");
 341         }
 342         printram("\n");
 343
 344         /*  Module Thermal Sensor */
 345         reg8 = spd[32];
 346         if (reg8 & 0x80)
 347                 dimm->flags.therm_sensor = 1;
 348         printram("  Thermal sensor     : %s\n", dimm->flags.therm_sensor ? "yes" : "no");
 349
 350         /*  SDRAM Device Type */
 351         printram("  Standard SDRAM     : %s\n", (spd[33] & 0x80) ? "no" : "yes");
 352
 353         if (spd[63] & 0x01) {
 354                 dimm->flags.pins_mirrored = 1;
 355         }
 356         printram("  Rank1 Address bits : %s\n", (spd[63] & 0x01) ? "mirrored" : "normal");
 357
 358         dimm->reference_card = spd[62] & 0x1f;
 359         printram("  DIMM Reference card: %c\n", 'A' + dimm->reference_card);
 360
 361         dimm->manufacturer_id = (spd[118] << 8) | spd[117];
 362         printram("  Manufacturer ID    : %x\n", dimm->manufacturer_id);
 363
 364         dimm->part_number[16] = 0;
 365         memcpy(dimm->part_number, &spd[128], 16);
 366         printram("  Part number        : %s\n", dimm->part_number);
 367
 368         memcpy(dimm->serial, &spd[SPD_DIMM_SERIAL_NUM], SPD_DIMM_SERIAL_LEN);
 369
 370         return ret;
 371 }
 372
 373 /**
 374  * \brief Decode the raw SPD XMP data
 375  *
 376  * Decodes a raw SPD XMP data from a DDR3 DIMM, and organizes it into a
 377  * @ref dimm_attr structure. The SPD data must first be read in a contiguous
 378  * array, and passed to this function.
 379  *
 380  * @param dimm pointer to @ref dimm_attr structure where the decoded data is to
 381  *        be stored
 382  * @param spd array of raw data previously read from the SPD.
 383  *
 384  * @param profile select one of the profiles to load
 385  *
 386  * @return @ref spd_status enumerator
 387  *              SPD_STATUS_OK -- decoding was successful
 388  *              SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD
 389  *              SPD_STATUS_CRC_ERROR -- CRC did not verify
 390  *              SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
 391  *                                          detected.
 392  */
 393 int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd,
 394                         enum ddr3_xmp_profile profile)
 395 {
 396         int ret;
 397         u32 mtb; /* medium time base */
 398         u8 *xmp; /* pointer to XMP profile data */
 399
 400         /* need a valid SPD */
 401         ret = spd_decode_ddr3(dimm, spd);
 402         if (ret != SPD_STATUS_OK)
 403                 return ret;
 404
 405         /* search for magic header */
 406         if (spd[176] != 0x0C || spd[177] != 0x4A) {
 407                 printram("Not a DDR3 XMP profile!\n");
 408                 dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 409                 return SPD_STATUS_INVALID;
 410         }
 411
 412         if (profile == DDR3_XMP_PROFILE_1) {
 413                 if (!(spd[178] & 1)) {
 414                         printram("Selected XMP profile disabled!\n");
 415                         dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 416                         return SPD_STATUS_INVALID;
 417                 }
 418
 419                 printram("  XMP Profile        : 1\n");
 420                 xmp = &spd[185];
 421
 422                 /* Medium Timebase =
 423                  *   Medium Timebase (MTB) Dividend /
 424                  *   Medium Timebase (MTB) Divisor */
 425                 mtb = (((u32)spd[180]) << 8) / spd[181];
 426
 427                 dimm->dimms_per_channel = ((spd[178] >> 2) & 0x3) + 1;
 428         } else {
 429                 if (!(spd[178] & 2)) {
 430                         printram("Selected XMP profile disabled!\n");
 431                         dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 432                         return SPD_STATUS_INVALID;
 433                 }
 434                 printram("  XMP Profile        : 2\n");
 435                 xmp = &spd[220];
 436
 437                 /* Medium Timebase =
 438                  *   Medium Timebase (MTB) Dividend /
 439                  *   Medium Timebase (MTB) Divisor */
 440                 mtb = (((u32)spd[182]) << 8) / spd[183];
 441
 442                 dimm->dimms_per_channel = ((spd[178] >> 4) & 0x3) + 1;
 443         }
 444
 445         printram("  Max DIMMs/channel  : %u\n", dimm->dimms_per_channel);
 446
 447         printram("  XMP Revision       : %u.%u\n", spd[179] >> 4, spd[179] & 0xf);
 448
 449         /* calculate voltage in mV */
 450         dimm->voltage = (xmp[0] & 1) * 50;
 451         dimm->voltage += ((xmp[0] >> 1) & 0xf) * 100;
 452         dimm->voltage += ((xmp[0] >> 5) & 0x3) * 1000;
 453
 454         printram("  Requested voltage  : %u mV\n", dimm->voltage);
 455
 456         /* SDRAM Minimum Cycle Time (tCKmin) */
 457         dimm->tCK = xmp[1] * mtb;
 458         /* CAS Latencies Supported */
 459         dimm->cas_supported = ((xmp[4] << 8) + xmp[3]) & 0x7fff;
 460         /* Minimum CAS Latency Time (tAAmin) */
 461         dimm->tAA = xmp[2] * mtb;
 462         /* Minimum Write Recovery Time (tWRmin) */
 463         dimm->tWR = xmp[8] * mtb;
 464         /* Minimum RAS# to CAS# Delay Time (tRCDmin) */
 465         dimm->tRCD = xmp[7] * mtb;
 466         /* Minimum Row Active to Row Active Delay Time (tRRDmin) */
 467         dimm->tRRD = xmp[17] * mtb;
 468         /* Minimum Row Precharge Delay Time (tRPmin) */
 469         dimm->tRP = xmp[6] * mtb;
 470         /* Minimum Active to Precharge Delay Time (tRASmin) */
 471         dimm->tRAS = (((xmp[9] & 0x0f) << 8) + xmp[10]) * mtb;
 472         /* Minimum Active to Active/Refresh Delay Time (tRCmin) */
 473         dimm->tRC = (((xmp[9] & 0xf0) << 4) + xmp[11]) * mtb;
 474         /* Minimum Refresh Recovery Delay Time (tRFCmin) */
 475         dimm->tRFC = ((xmp[15] << 8) + xmp[14]) * mtb;
 476         /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */
 477         dimm->tWTR = xmp[20] * mtb;
 478         /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */
 479         dimm->tRTP = xmp[16] * mtb;
 480         /* Minimum Four Activate Window Delay Time (tFAWmin) */
 481         dimm->tFAW = (((xmp[18] & 0x0f) << 8) + xmp[19]) * mtb;
 482         /* Minimum CAS Write Latency Time (tCWLmin) */
 483         dimm->tCWL = xmp[5] * mtb;
 484         /* System CMD Rate Mode */
 485         dimm->tCMD = xmp[23] * mtb;
 486
 487         return ret;
 488 }
 489
 490 /**
 491  * Fill cbmem with information for SMBIOS type 17.
 492  *
 493  * @param channel Corresponding channel of provided @info
 494  * @param slot Corresponding slot of provided @info
 495  * @param selected_freq The actual frequency the DRAM is running on
 496  * @param info DIMM parameters read from SPD
 497  *
 498  * @return CB_SUCCESS if DIMM info was written
 499  */
 500 enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq,
 501                              const struct dimm_attr_ddr3_st *info)
 502 {
 503         struct memory_info *mem_info;
 504         struct dimm_info *dimm;
 505
 506         /*
 507          * Allocate CBMEM area for DIMM information used to populate SMBIOS
 508          * table 17
 509          */
 510         mem_info = cbmem_find(CBMEM_ID_MEMINFO);
 511         if (!mem_info) {
 512                 mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
 513
 514                 printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info);
 515                 if (!mem_info)
 516                         return CB_ERR;
 517
 518                 memset(mem_info, 0, sizeof(*mem_info));
 519         }
 520
 521         if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) {
 522                 printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n", __func__);
 523                 return CB_ERR;
 524         }
 525
 526         dimm = &mem_info->dimm[mem_info->dimm_cnt];
 527         if (info->size_mb) {
 528                 dimm->ddr_type = MEMORY_TYPE_DDR3;
 529                 dimm->ddr_frequency = selected_freq;
 530                 dimm->dimm_size = info->size_mb;
 531                 dimm->channel_num = channel;
 532                 dimm->rank_per_dimm = info->ranks;
 533                 dimm->dimm_num = slot;
 534                 memcpy(dimm->module_part_number, info->part_number, 16);
 535                 dimm->mod_id = info->manufacturer_id;
 536                 dimm->mod_type = info->dimm_type;
 537                 dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only
 538                 memcpy(dimm->serial, info->serial,
 539                        MIN(sizeof(dimm->serial), sizeof(info->serial)));
 540                 mem_info->dimm_cnt++;
 541         }
 542
 543         return CB_SUCCESS;
 544 }
 545
 546 /*
 547  * The information printed below has a more informational character, and is not
 548  * necessarily tied in to RAM init debugging. Hence, we stop using printram(),
 549  * and use the standard printk()'s below.
 550  */
 551
 552 static void print_ns(const char *msg, u32 val)
 553 {
 554         u32 mant, fp;
 555         mant = val / 256;
 556         fp = (val % 256) * 1000 / 256;
 557
 558         printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp);
 559 }
 560
 561 /**
 562 * \brief Print the info in DIMM
 563 *
 564 * Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is
 565 * selected, or for a purely informative output.
 566 *
 567 * @param dimm pointer to already decoded @ref dimm_attr structure
 568 */
 569 void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm)
 570 {
 571         u16 val16;
 572         int i;
 573
 574         printk(BIOS_INFO, "  Row    addr bits  : %u\n", dimm->row_bits);
 575         printk(BIOS_INFO, "  Column addr bits  : %u\n", dimm->col_bits);
 576         printk(BIOS_INFO, "  Number of ranks   : %u\n", dimm->ranks);
 577         printk(BIOS_INFO, "  DIMM Capacity     : %u MB\n", dimm->size_mb);
 578
 579         /* CAS Latencies Supported */
 580         val16 = dimm->cas_supported;
 581         printk(BIOS_INFO, "  CAS latencies     :");
 582         i = 0;
 583         do {
 584                 if (val16 & 1)
 585                         printk(BIOS_INFO, " %u", i + 4);
 586                 i++;
 587                 val16 >>= 1;
 588         } while (val16);
 589         printk(BIOS_INFO, "\n");
 590
 591         print_ns("  tCKmin            : ", dimm->tCK);
 592         print_ns("  tAAmin            : ", dimm->tAA);
 593         print_ns("  tWRmin            : ", dimm->tWR);
 594         print_ns("  tRCDmin           : ", dimm->tRCD);
 595         print_ns("  tRRDmin           : ", dimm->tRRD);
 596         print_ns("  tRPmin            : ", dimm->tRP);
 597         print_ns("  tRASmin           : ", dimm->tRAS);
 598         print_ns("  tRCmin            : ", dimm->tRC);
 599         print_ns("  tRFCmin           : ", dimm->tRFC);
 600         print_ns("  tWTRmin           : ", dimm->tWTR);
 601         print_ns("  tRTPmin           : ", dimm->tRTP);
 602         print_ns("  tFAWmin           : ", dimm->tFAW);
 603         /* Those values are only relevant if an XMP profile sets them */
 604         if (dimm->tCWL)
 605                 print_ns("  tCWLmin           : ", dimm->tCWL);
 606         if (dimm->tCMD)
 607                 printk(BIOS_INFO, "  tCMDmin           : %3u\n", DIV_ROUND_UP(dimm->tCMD, 256));
 608 }