src/device/dram/ddr4.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <cbmem.h>
   5 #include <device/device.h>
   6 #include <device/dram/ddr4.h>
   7 #include <string.h>
   8 #include <memory_info.h>
   9 #include <smbios.h>
  10 #include <types.h>
  11
  12 enum ddr4_speed_grade {
  13         DDR4_1600,
  14         DDR4_1866,
  15         DDR4_2133,
  16         DDR4_2400,
  17         DDR4_2666,
  18         DDR4_2933,
  19         DDR4_3200
  20 };
  21
  22 struct ddr4_speed_attr {
  23         uint32_t min_clock_mhz; // inclusive
  24         uint32_t max_clock_mhz; // inclusive
  25         uint32_t reported_mts;
  26 };
  27
  28 /**
  29  * DDR4 speed attributes derived from JEDEC 79-4C tables 169 & 170
  30  *
  31  * min_clock_mhz = 1000/max_tCk_avg(ns) + 1
  32  *                 Adding 1 to make minimum inclusive
  33  * max_clock_mhz = 1000/min_tCk_avg(ns)
  34  * reported_mts  = Standard reported DDR4 speed in MT/s
  35  *                 May be 1 less than the actual max MT/s
  36  */
  37 static const struct ddr4_speed_attr ddr4_speeds[] = {
  38         [DDR4_1600] = {.min_clock_mhz =  668, .max_clock_mhz =  800, .reported_mts = 1600},
  39         [DDR4_1866] = {.min_clock_mhz =  801, .max_clock_mhz =  934, .reported_mts = 1866},
  40         [DDR4_2133] = {.min_clock_mhz =  935, .max_clock_mhz = 1067, .reported_mts = 2133},
  41         [DDR4_2400] = {.min_clock_mhz = 1068, .max_clock_mhz = 1200, .reported_mts = 2400},
  42         [DDR4_2666] = {.min_clock_mhz = 1201, .max_clock_mhz = 1333, .reported_mts = 2666},
  43         [DDR4_2933] = {.min_clock_mhz = 1334, .max_clock_mhz = 1466, .reported_mts = 2933},
  44         [DDR4_3200] = {.min_clock_mhz = 1467, .max_clock_mhz = 1600, .reported_mts = 3200}
  45 };
  46
  47 typedef enum {
  48         BLOCK_0, /* Base Configuration and DRAM Parameters */
  49         BLOCK_1,
  50         BLOCK_1_L, /* Standard Module Parameters */
  51         BLOCK_1_H, /* Hybrid Module Parameters */
  52         BLOCK_2,
  53         BLOCK_2_L, /* Hybrid Module Extended Function Parameters */
  54         BLOCK_2_H, /* Manufacturing Information */
  55         BLOCK_3    /* End user programmable */
  56 } spd_block_type;
  57
  58 typedef struct {
  59         spd_block_type type;
  60         uint16_t start;     /* starting offset from beginning of the spd */
  61         uint16_t len;       /* size of the block */
  62         uint16_t crc_start; /* offset from start of crc bytes, 0 if none */
  63 } spd_block;
  64
  65 /* 'SPD contents architecture' as per datasheet */
  66 const spd_block spd_blocks[] = {
  67         {.type = BLOCK_0, 0, 128, 126},   {.type = BLOCK_1, 128, 128, 126},
  68         {.type = BLOCK_1_L, 128, 64, 0},  {.type = BLOCK_1_H, 192, 64, 0},
  69         {.type = BLOCK_2_L, 256, 64, 62}, {.type = BLOCK_2_H, 320, 64, 0},
  70         {.type = BLOCK_3, 384, 128, 0}
  71 };
  72
  73 static bool verify_block(const spd_block *block, spd_raw_data spd)
  74 {
  75         uint16_t crc, spd_crc;
  76
  77         spd_crc = (spd[block->start + block->crc_start + 1] << 8) |
  78                   spd[block->start + block->crc_start];
  79         crc = ddr_crc16(&spd[block->start], block->len - 2);
  80
  81         return spd_crc == crc;
  82 }
  83
  84 /* Check if given block is 'reserved' for a given module type */
  85 static bool block_exists(spd_block_type type, u8 dimm_type)
  86 {
  87         bool is_hybrid;
  88
  89         switch (type) {
  90         case BLOCK_0: /* fall-through */
  91         case BLOCK_1: /* fall-through */
  92         case BLOCK_1_L: /* fall-through */
  93         case BLOCK_1_H: /* fall-through */
  94         case BLOCK_2_H: /* fall-through */
  95         case BLOCK_3: /* fall-through */
  96                 return true;
  97         case BLOCK_2_L:
  98                 is_hybrid = (dimm_type >> 4) & ((1 << 3) - 1);
  99                 if (is_hybrid)
 100                         return true;
 101                 return false;
 102         default: /* fall-through */
 103                 return false;
 104         }
 105 }
 106
 107 /**
 108  * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s
 109  */
 110 uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz)
 111 {
 112         for (enum ddr4_speed_grade speed = 0; speed < ARRAY_SIZE(ddr4_speeds); speed++) {
 113                 const struct ddr4_speed_attr *speed_attr = &ddr4_speeds[speed];
 114                 if (speed_mhz >= speed_attr->min_clock_mhz &&
 115                     speed_mhz <= speed_attr->max_clock_mhz) {
 116                         return speed_attr->reported_mts;
 117                 }
 118         }
 119         printk(BIOS_ERR, "DDR4 speed of %d MHz is out of range\n", speed_mhz);
 120         return 0;
 121 }
 122
 123 /**
 124  * \brief Decode the raw SPD data
 125  *
 126  * Decodes a raw SPD data from a DDR4 DIMM, and organizes it into a
 127  * @ref dimm_attr structure. The SPD data must first be read in a contiguous
 128  * array, and passed to this function.
 129  *
 130  * @param dimm pointer to @ref dimm_attr structure where the decoded data is to
 131  *             be stored
 132  * @param spd array of raw data previously read from the SPD.
 133  *
 134  * @return @ref spd_status enumerator
 135  *              SPD_STATUS_OK -- decoding was successful
 136  *              SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD
 137  *              SPD_STATUS_CRC_ERROR -- checksum mismatch
 138  */
 139 int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd)
 140 {
 141         u8 reg8;
 142         u8 bus_width, sdram_width;
 143         u16 cap_per_die_mbit;
 144         u16 spd_bytes_total, spd_bytes_used;
 145         const uint16_t spd_bytes_used_table[] = {0, 128, 256, 384, 512};
 146
 147         /* Make sure that the SPD dump is indeed from a DDR4 module */
 148         if (spd[2] != SPD_MEMORY_TYPE_DDR4_SDRAM) {
 149                 printk(BIOS_ERR, "Not a DDR4 SPD!\n");
 150                 dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 151                 return SPD_STATUS_INVALID;
 152         }
 153
 154         spd_bytes_total = (spd[0] >> 4) & 0x7;
 155         spd_bytes_used = spd[0] & 0xf;
 156
 157         if (!spd_bytes_total || !spd_bytes_used) {
 158                 printk(BIOS_ERR, "SPD failed basic sanity checks\n");
 159                 return SPD_STATUS_INVALID;
 160         }
 161
 162         if (spd_bytes_total >= 3)
 163                 printk(BIOS_WARNING, "SPD Bytes Total value is reserved\n");
 164
 165         spd_bytes_total = 256 << (spd_bytes_total - 1);
 166
 167         if (spd_bytes_used > 4) {
 168                 printk(BIOS_ERR, "SPD Bytes Used value is reserved\n");
 169                 return SPD_STATUS_INVALID;
 170         }
 171
 172         spd_bytes_used = spd_bytes_used_table[spd_bytes_used];
 173
 174         if (spd_bytes_used > spd_bytes_total) {
 175                 printk(BIOS_ERR, "SPD Bytes Used is greater than SPD Bytes Total\n");
 176                 return SPD_STATUS_INVALID;
 177         }
 178
 179         /* Verify CRC of blocks that have them, do not step over 'used' length */
 180         for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) {
 181                 /* this block is not checksummed */
 182                 if (spd_blocks[i].crc_start == 0)
 183                         continue;
 184                 /* we shouldn't have this block */
 185                 if (spd_blocks[i].start + spd_blocks[i].len > spd_bytes_used)
 186                         continue;
 187                 /* check if block exists in the current schema */
 188                 if (!block_exists(spd_blocks[i].type, spd[3]))
 189                         continue;
 190                 if (!verify_block(&spd_blocks[i], spd)) {
 191                         printk(BIOS_ERR, "CRC failed for block %d\n", i);
 192                         return SPD_STATUS_CRC_ERROR;
 193                 }
 194         }
 195
 196         dimm->dram_type = SPD_MEMORY_TYPE_DDR4_SDRAM;
 197         dimm->dimm_type = spd[3] & ((1 << 4) - 1);
 198
 199         reg8 = spd[13] & ((1 << 4) - 1);
 200         dimm->bus_width = reg8;
 201         bus_width = 8 << (reg8 & ((1 << 3) - 1));
 202
 203         reg8 = spd[12] & ((1 << 3) - 1);
 204         dimm->sdram_width = reg8;
 205         sdram_width = 4 << reg8;
 206
 207         reg8 = spd[4] & ((1 << 4) - 1);
 208         dimm->cap_per_die_mbit = reg8;
 209         cap_per_die_mbit = (1 << reg8) * 256;
 210
 211         reg8 = (spd[12] >> 3) & ((1 << 3) - 1);
 212         dimm->ranks = reg8 + 1;
 213
 214         if (!bus_width || !sdram_width) {
 215                 printk(BIOS_ERR, "SPD information is invalid");
 216                 dimm->size_mb = 0;
 217                 return SPD_STATUS_INVALID;
 218         }
 219
 220         /* seems to be only one, in mV */
 221         dimm->vdd_voltage = 1200;
 222
 223         /* calculate size */
 224         /* FIXME: this is wrong for 3DS devices */
 225         dimm->size_mb = cap_per_die_mbit / 8 * bus_width / sdram_width * dimm->ranks;
 226
 227         dimm->ecc_extension = spd[SPD_PRIMARY_SDRAM_WIDTH] & SPD_ECC_8BIT;
 228
 229         /* make sure we have the manufacturing information block */
 230         if (spd_bytes_used > 320) {
 231                 dimm->manufacturer_id = (spd[351] << 8) | spd[350];
 232                 memcpy(dimm->part_number, &spd[329], SPD_DDR4_PART_LEN);
 233                 dimm->part_number[SPD_DDR4_PART_LEN] = 0;
 234                 memcpy(dimm->serial_number, &spd[325], sizeof(dimm->serial_number));
 235         }
 236         return SPD_STATUS_OK;
 237 }
 238
 239 enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq,
 240                                   const struct dimm_attr_ddr4_st *info)
 241 {
 242         struct memory_info *mem_info;
 243         struct dimm_info *dimm;
 244
 245         /*
 246          * Allocate CBMEM area for DIMM information used to populate SMBIOS
 247          * table 17
 248          */
 249         mem_info = cbmem_find(CBMEM_ID_MEMINFO);
 250         if (!mem_info) {
 251                 mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
 252
 253                 printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info);
 254                 if (!mem_info)
 255                         return CB_ERR;
 256
 257                 memset(mem_info, 0, sizeof(*mem_info));
 258         }
 259
 260         if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) {
 261                 printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n", __func__);
 262                 return CB_ERR;
 263         }
 264
 265         dimm = &mem_info->dimm[mem_info->dimm_cnt];
 266         if (info->size_mb) {
 267                 dimm->ddr_type = MEMORY_TYPE_DDR4;
 268                 dimm->ddr_frequency = selected_freq;
 269                 dimm->dimm_size = info->size_mb;
 270                 dimm->channel_num = channel;
 271                 dimm->rank_per_dimm = info->ranks;
 272                 dimm->dimm_num = slot;
 273                 memcpy(dimm->module_part_number, info->part_number, SPD_DDR4_PART_LEN);
 274                 dimm->mod_id = info->manufacturer_id;
 275
 276                 switch (info->dimm_type) {
 277                 case SPD_DDR4_DIMM_TYPE_SO_DIMM:
 278                         dimm->mod_type = DDR4_SPD_SODIMM;
 279                         break;
 280                 case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM:
 281                         dimm->mod_type = DDR4_SPD_72B_SO_RDIMM;
 282                         break;
 283                 case SPD_DDR4_DIMM_TYPE_UDIMM:
 284                         dimm->mod_type = DDR4_SPD_UDIMM;
 285                         break;
 286                 case SPD_DDR4_DIMM_TYPE_RDIMM:
 287                         dimm->mod_type = DDR4_SPD_RDIMM;
 288                         break;
 289                 default:
 290                         dimm->mod_type = SPD_UNDEFINED;
 291                         break;
 292                 }
 293
 294                 dimm->bus_width = info->bus_width;
 295                 memcpy(dimm->serial, info->serial_number,
 296                        MIN(sizeof(dimm->serial), sizeof(info->serial_number)));
 297
 298                 dimm->vdd_voltage = info->vdd_voltage;
 299                 mem_info->dimm_cnt++;
 300         }
 301
 302         return CB_SUCCESS;
 303 }