soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
[coreboot.git] / src / drivers / amd / agesa / bootblock.c
blobc2934819844dafea61c486dff403d0cc35650b33
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootblock_common.h>
4 #include <halt.h>
5 #include <amdblocks/amd_pci_mmconf.h>
6 #include <amdblocks/biosram.h>
7 #include <arch/bootblock.h>
8 #include <cpu/x86/mtrr.h>
9 #include <cpu/x86/lapic.h>
11 #define EARLY_VMTRR_FLASH 6
13 static void set_early_mtrrs(void)
15 /* Cache the ROM to speed up booting */
16 set_var_mtrr(EARLY_VMTRR_FLASH, OPTIMAL_CACHE_ROM_BASE,
17 OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
20 void bootblock_soc_early_init(void)
22 bootblock_early_southbridge_init();
25 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
27 enable_pci_mmconf();
28 set_early_mtrrs();
30 if (CONFIG(UDELAY_LAPIC))
31 enable_lapic();
33 bootblock_main_with_basetime(base_timestamp);
36 asmlinkage void ap_bootblock_c_entry(void)
38 enable_pci_mmconf();
39 set_early_mtrrs();
41 if (CONFIG(UDELAY_LAPIC))
42 enable_lapic();
44 void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
45 ap_romstage_entry(); /* execution does not return */
46 halt();