soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
[coreboot.git] / src / drivers / amd / agesa / cache_as_ram.S
blobe3420397b1e9836ce4f430adc3e6d2622f8fb31b
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /******************************************************************************
4  * AMD Generic Encapsulated Software Architecture
5  *
6  * $Workfile:: cache_as_ram.S
7  *
8  * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler
9  *
10  ******************************************************************************
11  */
13 #include <cpu/x86/lapic_def.h>
14 #include <cpu/x86/post_code.h>
15 #include <amdblocks/post_codes.h>
17 .section .init
19 .code32
21 .global bootblock_pre_c_entry
23 _cache_as_ram_setup:
25 #include "gcccar.inc"
28  * on entry:
29  *   mm0: BIST (ignored)
30  *   mm2_mm1: timestamp
31  */
32 bootblock_pre_c_entry:
34         post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
36         AMD_ENABLE_STACK
38         /*
39          * Set up bootblock stack on BSP.
40          * AMD_ENABLE_STACK macro sets up a stack for BSP at BSP_STACK_BASE_ADDR
41          * which is 0x30000 (_car_region_end), but for C bootblock the stack
42          * begins at _ecar_stack (see arch/x86/car.ld)
43          */
44         mov     $LAPIC_BASE_MSR, %ecx
45         rdmsr
46         test    $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
47         jz      ap_entry
49         mov     $_ecar_stack, %esp
51         /* Align the stack and keep aligned for call to bootblock_c_entry() */
52         and     $0xfffffff0, %esp
53         sub     $8, %esp
55         movd    %mm2, %eax
56         pushl   %eax            /* tsc[63:32] */
57         movd    %mm1, %eax
58         pushl   %eax            /* tsc[31:0] */
60         post_code(POST_BOOTBLOCK_PRE_C_DONE)
62         call    bootblock_c_entry
64         /* Never reached. */
66 stop:
67         post_code(POST_DEAD_CODE)
68         hlt
69         jmp     stop
71 ap_entry:
72         /* Align the stack for call to ap_bootblock_c_entry() */
73         and     $0xfffffff0, %esp
74         call    ap_bootblock_c_entry
76         /* Never reached. */
77         jmp     stop
79 _cache_as_ram_setup_end: