1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /******************************************************************************
4 * AMD Generic Encapsulated Software Architecture
6 * $Workfile:: cache_as_ram.S
8 * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler
10 ******************************************************************************
13 #include <cpu/x86/lapic_def.h>
14 #include <cpu/x86/post_code.h>
15 #include <amdblocks/post_codes.h>
21 .global bootblock_pre_c_entry
32 bootblock_pre_c_entry:
34 post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
39 * Set up bootblock stack on BSP.
40 * AMD_ENABLE_STACK macro sets up a stack for BSP at BSP_STACK_BASE_ADDR
41 * which is 0x30000 (_car_region_end), but for C bootblock the stack
42 * begins at _ecar_stack (see arch/x86/car.ld)
44 mov $LAPIC_BASE_MSR, %ecx
46 test $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
49 mov $_ecar_stack, %esp
51 /* Align the stack and keep aligned for call to bootblock_c_entry() */
56 pushl %eax /* tsc[63:32] */
58 pushl %eax /* tsc[31:0] */
60 post_code(POST_BOOTBLOCK_PRE_C_DONE)
62 call bootblock_c_entry
67 post_code(POST_DEAD_CODE)
72 /* Align the stack for call to ap_bootblock_c_entry() */
74 call ap_bootblock_c_entry
79 _cache_as_ram_setup_end: