soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
[coreboot.git] / src / drivers / amd / agesa / oem_s3.c
blobeacb5233d918545351dd3618f008925d7f60e2b8
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <string.h>
4 #include <cbmem.h>
5 #include <console/console.h>
6 #include <mrc_cache.h>
7 #include <northbridge/amd/agesa/state_machine.h>
8 #include <AGESA.h>
9 #include <northbridge/amd/agesa/agesa_helper.h>
11 /* Training data versioning is not supported or tracked. */
12 #define DEFAULT_MRC_VERSION 0
14 AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock)
16 void *nv_storage = NULL;
17 size_t nv_storage_size = 0;
19 nv_storage = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION,
20 &nv_storage_size);
22 if (nv_storage == NULL || nv_storage_size == 0) {
23 printk(BIOS_ERR, "%s: No valid MRC cache!\n", __func__);
24 return AGESA_CRITICAL;
27 dataBlock->NvStorage = nv_storage;
28 dataBlock->NvStorageSize = nv_storage_size;
30 return AGESA_SUCCESS;
33 AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock)
35 char *heap = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
36 if (heap == NULL)
37 return AGESA_FATAL;
39 printk(BIOS_DEBUG, "Using resume HEAP at %08x\n",
40 (unsigned int)(uintptr_t)heap);
42 /* Return allocated CBMEM size, we do not keep track of
43 * how much was actually used.
45 dataBlock->VolatileStorageSize = HIGH_MEMORY_SCRATCH;
46 dataBlock->VolatileStorage = heap;
47 return AGESA_SUCCESS;
50 AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock)
52 if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION,
53 dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) {
54 printk(BIOS_ERR, "%s: Failed to stash MRC data\n", __func__);
55 return AGESA_CRITICAL;
58 /* To be consumed in AmdS3LateRestore. */
59 char *heap = cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH);
60 if (heap) {
61 memset(heap, 0, HIGH_MEMORY_SCRATCH);
62 memcpy(heap, dataBlock->VolatileStorage, dataBlock->VolatileStorageSize);
65 /* Collect MTRR setup. */
66 backup_mtrr();
68 return AGESA_SUCCESS;