soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
[coreboot.git] / src / drivers / crb / tpm.h
blobbe26be2d24ff07330cbe0bf1386ac6a3f23c85ae
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* This is a driver for a Command Response Buffer Interface */
4 /* CRB driver */
5 /* address of locality 0 (CRB) */
6 #define TPM_CRB_BASE_ADDRESS CONFIG_CRB_TPM_BASE_ADDRESS
8 #define CRB_REG(LOCTY, REG) \
9 (void *)(uintptr_t)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG)
11 /* hardware registers */
12 #define CRB_REG_LOC_STATE 0x00
13 #define CRB_REG_LOC_CTRL 0x08
14 #define CRB_REG_LOC_STS 0x0C
16 /* LOC_CTRL BIT MASKS */
17 #define LOC_CTRL_REQ_ACCESS 0x01
19 /* LOC STATE BIT MASKS */
20 #define LOC_STATE_LOC_ASSIGN 0x02
21 #define LOC_STATE_REG_VALID_STS 0x80
23 /* LOC STS BIT MASKS */
24 #define LOC_STS_GRANTED 0x01
26 #define CRB_REG_INTF_ID 0x30
27 #define CRB_REG_REQUEST 0x40
28 #define CRB_REG_STATUS 0x44
29 #define CRB_REG_CANCEL 0x48
30 #define CRB_REG_START 0x4C
31 #define CRB_REG_INT_CTRL 0x50
32 #define CRB_REG_CMD_SIZE 0x58
33 #define CRB_REG_CMD_ADDR 0x5C
34 #define CRB_REG_RESP_SIZE 0x64
35 #define CRB_REG_RESP_ADDR 0x68
36 #define CRB_REG_DATA_BUFF 0x80
38 /* CRB INTF BIT MASK */
39 #define CRB_INTF_REG_CAP_CRB (1<<14)
40 #define CRB_INTF_REG_INTF_SEL (1<<17)
41 #define CRB_INTF_REG_INTF_LOCK (1<<19)
43 /*REQUEST Register related */
44 #define CRB_REG_REQUEST_CMD_RDY 0x01
45 #define CRB_REG_REQUEST_GO_IDLE 0x02
47 /* STATUS Register related */
48 #define CRB_REG_STATUS_ERROR 0x01
49 #define CRB_REG_STATUS_IDLE 0x02
51 /* START Register related */
52 #define CRB_REG_START_START 0x01
54 /* TPM Info Struct */
55 struct tpm2_info {
56 uint16_t vendor_id;
57 uint16_t device_id;
58 uint16_t revision;
61 int tpm2_init(void);
62 void tpm2_get_info(struct tpm2_info *tpm2_info);
63 size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
64 void *tpm2_response, size_t max_response);