soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
[coreboot.git] / src / drivers / generic / bayhub / bh720.h
blobcc5fbea07bb403da9355b560d80130517b8d6bde
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */
5 #include <types.h>
7 enum {
8 BH720_PROTECT = 0xd0,
9 BH720_PROTECT_LOCK_OFF = 0,
10 BH720_PROTECT_LOCK_ON = BIT(0),
11 BH720_PROTECT_OFF = 0,
12 BH720_PROTECT_ON = BIT(31),
14 BH720_LINK_CTRL = 0x90,
15 BH720_LINK_CTRL_L0_ENABLE = BIT(0),
16 BH720_LINK_CTRL_L1_ENABLE = BIT(1),
17 BH720_LINK_CTRL_CLKREQ = BIT(8),
19 BH720_MISC2 = 0xf0,
20 BH720_MISC2_ASPM_DISABLE = BIT(0),
21 BH720_MISC2_APSM_CLKREQ_L1 = BIT(7),
22 BH720_MISC2_APSM_PHY_L1 = BIT(10),
23 BH720_MISC2_APSM_MORE = BIT(12),
25 BH720_MEM_RW_DATA = 0x200,
26 BH720_MEM_RW_ADR = 0x204,
27 BH720_MEM_RW_READ = BIT(30),
28 BH720_MEM_RW_WRITE = BIT(31),
29 BH720_MEM_ACCESS_EN = 0x208,
30 BH720_PCR_DrvStrength_PLL = 0x304,
31 BH720_PCR_DATA_CMD_DRV_MAX = 7,
32 BH720_PCR_CLK_DRV_MAX = 7,
33 BH720_PCR_EMMC_SETTING = 0x308,
34 BH720_PCR_EMMC_SETTING_1_8V = BIT(4),
36 BH720_RTD3_L1 = 0x3e0,
37 BH720_RTD3_L1_DISABLE_L1 = BIT(28),
39 BH720_PCR_CSR = 0x3e4,
40 BH720_PCR_CSR_EMMC_MODE_SEL = BIT(22),