src/drivers/generic/bayhub_lv2/lv2.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* Driver for BayHub Technology LV2 PCI to SD bridge */
   4
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/path.h>
   8 #include <device/pci.h>
   9 #include <device/pciexp.h>
  10 #include <device/pci_ops.h>
  11 #include <device/pci_ids.h>
  12 #include "chip.h"
  13 #include "lv2.h"
  14
  15 /*
  16  * This chip has an errata where PCIe config space registers 0x234, 0x248, and
  17  * 0x24C only support DWORD access, therefore reprogram these in the `finalize`
  18  * callback.
  19  */
  20 static void lv2_enable_ltr(struct device *dev)
  21 {
  22         u16 max_snoop, max_nosnoop;
  23         if (!pciexp_get_ltr_max_latencies(dev, &max_snoop, &max_nosnoop))
  24                 return;
  25
  26         const unsigned int ltr_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID, 0);
  27         if (!ltr_cap)
  28                 return;
  29
  30         pci_write_config32(dev, ltr_cap + PCI_LTR_MAX_SNOOP, (max_snoop << 16) |  max_nosnoop);
  31         printk(BIOS_INFO, "%s: Re-programmed LTR max latencies using chip-specific quirk\n",
  32                dev_path(dev));
  33 }
  34
  35 static void lv2_enable(struct device *dev)
  36 {
  37         struct drivers_generic_bayhub_lv2_config *config = dev->chip_info;
  38         pci_dev_init(dev);
  39
  40         if (!config || !config->enable_power_saving)
  41                 return;
  42         /*
  43          * This procedure for enabling power-saving mode is from the
  44          * BayHub BIOS Implementation Guideline document.
  45          */
  46         pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_OFF | LV2_PROTECT_LOCK_OFF);
  47         pci_or_config32(dev, LV2_PCR_HEX_FC, LV2_PCIE_PHY_P1_ENABLE);
  48         pci_update_config32(dev, LV2_PCR_HEX_E0, LV2_PCI_PM_L1_TIMER_MASK, LV2_PCI_PM_L1_TIMER);
  49         pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER);
  50         pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE);
  51         pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING);
  52         pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK,
  53                             LV2_L1_SUBSTATE_OPTIMISE);
  54         pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW);
  55         pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK,
  56                             LV2_DRIVER_STRENGTH);
  57         pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK,
  58                             LV2_RESET_DMA_DISABLE);
  59         pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON);
  60         printk(BIOS_INFO, "BayHub LV2: Power-saving enabled\n");
  61 }
  62
  63 static struct device_operations lv2_ops = {
  64         .read_resources         = pci_dev_read_resources,
  65         .set_resources          = pci_dev_set_resources,
  66         .enable_resources       = pci_dev_enable_resources,
  67         .ops_pci                = &pci_dev_ops_pci,
  68         .enable                 = lv2_enable,
  69         .final                  = lv2_enable_ltr,
  70 };
  71
  72 static const unsigned short pci_device_ids[] = {
  73         PCI_DID_O2_LV2,
  74         0
  75 };
  76
  77 static const struct pci_driver bayhub_lv2 __pci_driver = {
  78         .ops            = &lv2_ops,
  79         .vendor         = PCI_VID_O2,
  80         .devices        = pci_device_ids,
  81 };
  82
  83 struct chip_operations drivers_generic_bayhub_lv2_ops = {
  84         CHIP_NAME("BayHub Technology LV2 PCIe to SD bridge")
  85 };