src/drivers/i2c/designware/dw_i2c.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __DRIVERS_I2C_DESIGNWARE_I2C_H__
   4 #define __DRIVERS_I2C_DESIGNWARE_I2C_H__
   5
   6 #include <device/device.h>
   7 #include <device/i2c.h>
   8 #include <types.h>
   9
  10 #if CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG)
  11 #define DW_I2C_DEBUG BIOS_DEBUG
  12
  13 #else
  14 #define DW_I2C_DEBUG BIOS_NEVER
  15
  16 #endif // CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG
  17
  18 /*
  19  * Timing values are in units of clock period, with the clock speed
  20  * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
  21  * Automatic configuration is done based on requested speed, but the
  22  * values may need tuned depending on the board and the number of
  23  * devices present on the bus.
  24  */
  25 struct dw_i2c_speed_config {
  26         enum i2c_speed speed;
  27         /* SCL high and low period count */
  28         uint16_t scl_lcnt;
  29         uint16_t scl_hcnt;
  30         /*
  31          * SDA hold time should be 300ns in standard and fast modes
  32          * and long enough for deterministic logic level change in
  33          * fast-plus and high speed modes.
  34          *
  35          *  [15:0] SDA TX Hold Time
  36          * [23:16] SDA RX Hold Time
  37          */
  38         uint32_t sda_hold;
  39 };
  40
  41 /*
  42  * This I2C controller has support for 3 independent speed configs but can
  43  * support both FAST_PLUS and HIGH speeds through the same set of speed
  44  * config registers.  These are treated separately so the speed config values
  45  * can be provided via ACPI to the OS.
  46  */
  47 #define DW_I2C_SPEED_CONFIG_COUNT       4
  48
  49 struct dw_i2c_bus_config {
  50         /* Bus should be enabled prior to ramstage with temporary base */
  51         int early_init;
  52         /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
  53         enum i2c_speed speed;
  54         /* If rise_time_ns is non-zero the calculations for lcnt and hcnt
  55          * registers take into account the times of the bus. However, if
  56          * there is a match in speed_config those register values take
  57          * precedence. */
  58         int rise_time_ns;
  59         int fall_time_ns;
  60         int data_hold_time_ns;
  61         /* Specific bus speed configuration */
  62         struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
  63 };
  64
  65 /* Functions to be implemented by SoC code */
  66
  67 /* Get base address for early init of I2C controllers. */
  68 uintptr_t dw_i2c_get_soc_early_base(unsigned int bus);
  69
  70 /*
  71  * Map given I2C bus number to devfn.
  72  * Return value:
  73  * -1 = error
  74  * otherwise, devfn(>=0) corresponding to I2C bus number.
  75  */
  76 int dw_i2c_soc_devfn_to_bus(unsigned int devfn);
  77
  78 /*
  79  * Map given bus number to a I2C Controller.
  80  * Return value:
  81  * -1 = error
  82  * otherwise, devfn(>=0) corresponding to I2C bus number.
  83  */
  84 int dw_i2c_soc_bus_to_devfn(unsigned int bus);
  85
  86 /*
  87  * SoC implemented callback for getting I2C bus configuration.
  88  *
  89  * Returns NULL if i2c config is not found
  90  */
  91 const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus);
  92
  93 /* Get I2C controller base address */
  94 uintptr_t dw_i2c_base_address(unsigned int bus);
  95
  96 /*
  97  * Initialize this bus controller and set the speed
  98 */
  99 enum cb_err dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg);
 100
 101 /*
 102  * Generate speed config based on clock
 103 */
 104 enum cb_err dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr,
 105                                         enum i2c_speed speed,
 106                                         const struct dw_i2c_bus_config *bcfg,
 107                                         struct dw_i2c_speed_config *config);
 108
 109 /*
 110  * Map an i2c host controller device to a logical bus number.
 111  * Return value:
 112  * -1 = failure
 113  * >=0 = logical bus number
 114  */
 115 int dw_i2c_soc_dev_to_bus(const struct device *dev);
 116
 117 /*
 118  * Common device_operations implementation to initialize the i2c host
 119  * controller.
 120  */
 121 void dw_i2c_dev_init(struct device *dev);
 122
 123 /*
 124  * Common device_operations implementation to fill ACPI SSDT table for i2c
 125  * host controller.
 126  */
 127 void dw_i2c_acpi_fill_ssdt(const struct device *dev);
 128
 129 /*
 130  * Common device_operations implementation for i2c host controller ops.
 131  */
 132 extern const struct i2c_bus_operations dw_i2c_bus_ops;
 133
 134 #endif /* __DRIVERS_I2C_DESIGNWARE_I2C_H__ */