1 # SPDX-License-Identifier: GPL-2.0-only
3 config PLATFORM_USES_FSP2_0
7 Include FSP 2.0 wrappers and functionality
9 config PLATFORM_USES_FSP2_1
12 select PLATFORM_USES_FSP2_0
13 select FSP_USES_CB_STACK
15 Include FSP 2.1 wrappers and functionality.
16 Feature added into FSP 2.1 specification that impacts coreboot is:
17 1. Remove FSP stack switch and use the same stack with boot firmware
19 config PLATFORM_USES_FSP2_2
22 select PLATFORM_USES_FSP2_1
24 Include FSP 2.2 wrappers and functionality.
25 Features added into FSP 2.2 specification that impact coreboot are:
26 1. Added multi-phase silicon initialization to increase the modularity of the
28 2. FSP_INFO_HEADER changes to add FspMultiPhaseSiInitEntryOffset
29 3. Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP2.0/2.1 can disable
30 the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change.
32 config PLATFORM_USES_FSP2_3
35 select PLATFORM_USES_FSP2_2
37 Include FSP 2.3 wrappers and functionality.
38 Features added into FSP 2.3 specification that impact coreboot are:
39 1. Added ExtendedImageRevision field in FSP_INFO_HEADER
40 2. Added FSP_NON_VOLATILE_STORAGE_HOB2
42 if PLATFORM_USES_FSP2_0
44 config PLATFORM_USES_FSP2_X86_32
48 The FSP 2.0 runs in x86_32 protected mode.
49 Once there's a x86_64 FSP this needs to default to n.
51 config HAVE_INTEL_FSP_REPO
54 Select this, if the FSP binaries for the platform are public
55 and available in 3rdparty/fsp/. When selecting this option, the
56 platform must also set FSP_HEADER_PATH and FSP_FD_PATH correctly.
59 bool "Use binaries of the Intel FSP repository on GitHub"
60 depends on HAVE_INTEL_FSP_REPO
64 Select this option to use the default FSP headers and binaries
65 found in the IntelFsp GitHub repository at
67 https://github.com/IntelFsp/FSP/
71 config FSP_HEADER_PATH
72 string "Location of FSP headers" if !FSP_USE_REPO
74 Include directory with the FSP ABI header files.
76 config ADD_FSP_BINARIES
77 bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO
78 default y if FSP_USE_REPO
80 Add the FSP-M and FSP-S binaries to CBFS.
83 string "Name of FSP-T in CBFS"
91 The location for FSP-T.
94 string "Name of FSP-S in CBFS"
98 string "Name of FSP-M in CBFS"
102 bool "Use a combined FSP FD file" if !FSP_USE_REPO
103 depends on ADD_FSP_BINARIES
105 Use a combined FSP FD file instead of specifying individual, already split
106 binaries and split the file at build-time.
109 string "Location of FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO
111 Path to the FSP FD file that contains the individual FSP-T, FSP-M
112 and FSP-S binaries. The file gets split at build-time.
115 string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD
116 depends on ADD_FSP_BINARIES
118 default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD
120 The path and filename of the Intel FSP-T binary for this platform.
123 string "Intel FSP-M (memory init) binary path and filename" if !FSP_FULL_FD
124 depends on ADD_FSP_BINARIES
125 default "\$(obj)/Fsp_M.fd" if FSP_FULL_FD
127 The path and filename of the Intel FSP-M binary for this platform.
130 string "Intel FSP-S (silicon init) binary path and filename" if !FSP_FULL_FD
131 depends on ADD_FSP_BINARIES
132 default "\$(obj)/Fsp_S.fd" if FSP_FULL_FD
134 The path and filename of the Intel FSP-S binary for this platform.
139 select NO_CBFS_MCACHE if !NO_FSP_TEMP_RAM_EXIT
141 Use FSP APIs to initialize & Tear Down the Cache-As-Ram
143 config FSP_T_RESERVED_SIZE
145 default 0x100 if FSP_CAR
148 This is the size of the area reserved by FSP-T. This is not
149 defined in the FSP specification but in the SOC integration
152 config NO_FSP_TEMP_RAM_EXIT
156 Select this on a platform where you want to use FSP-T but use
157 coreboot code to tear down CAR.
163 Select this value when FSP-M is execute-in-place.
169 Select this value when FSP-T is execute-in-place.
171 config FSP_USES_CB_STACK
175 Enable support for fsp to use same stack as coreboot.
176 This option allows fsp to continue using coreboot stack
177 without reinitializing stack pointer. This feature is
178 supported Icelake onwards.
180 config FSP_TEMP_RAM_SIZE
183 The amount of memory coreboot reserves for the FSP to use. In the
184 case of FSP 2.1 and newer that share the stack with coreboot instead
185 of having its own stack, this is the amount of anticipated heap usage
186 in CAR by FSP to setup HOB and needs to be the recommended value from
187 the Platform FSP integration guide. In the case of the FSP having its
188 own stack that will be placed in DRAM and not in CAR, this is the
189 amount of memory the FSP needs for its stack and heap.
191 config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
194 This is selected by SoC or mainboard to supply their own
195 concept of a version for the memory settings respectively.
196 This allows deployed systems to bump their version number
197 with the same FSP which will trigger a retrain of the memory.
199 config HAVE_FSP_LOGO_SUPPORT
206 depends on HAVE_FSP_LOGO_SUPPORT
208 Uses the FSP to display the boot logo. This method supports a
209 BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed
212 config FSP2_0_LOGO_FILE_NAME
215 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
217 config FSP_COMPRESS_FSP_S_LZMA
220 config FSP_COMPRESS_FSP_S_LZ4
223 config FSP_COMPRESS_FSP_M_LZMA
225 depends on !FSP_M_XIP
227 config FSP_COMPRESS_FSP_M_LZ4
229 depends on !FSP_M_XIP
231 config FSP_ALIGNMENT_FSP_S
234 Sets the CBFS alignment for FSP-S
236 config FSP_ALIGNMENT_FSP_M
239 Sets the CBFS alignment for FSP-M
244 The address FSP-M will be relocated to during build time
246 config FSP_STATUS_GLOBAL_RESET_REQUIRED_3
249 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
251 config FSP_STATUS_GLOBAL_RESET_REQUIRED_4
254 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
256 config FSP_STATUS_GLOBAL_RESET_REQUIRED_5
259 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
261 config FSP_STATUS_GLOBAL_RESET_REQUIRED_6
264 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
266 config FSP_STATUS_GLOBAL_RESET_REQUIRED_7
269 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
271 config FSP_STATUS_GLOBAL_RESET_REQUIRED_8
274 FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
276 config FSP_STATUS_GLOBAL_RESET
278 depends on SOC_INTEL_COMMON_FSP_RESET
279 default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3
280 default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4
281 default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5
282 default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6
283 default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7
284 default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8
287 If global reset is supported by SoC then select the correct status value for global
288 reset type from SoC Kconfig based on available Kconfig options
289 FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported.
291 config SOC_INTEL_COMMON_FSP_RESET
294 Common code block to handle platform reset request raised by FSP. The FSP
295 will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that
298 config FSPS_HAS_ARCH_UPD
301 SoC users must select this Kconfig if the `FSPS_UPD` header has architecture
302 UPD structure as `FSPS_ARCH_UPD`. Typically, platform with FSP 2.2 specification
303 onwards has support for `FSPS_ARCH_UPD` section as part of `FSPS_UPD` structure.
304 But there are some exceptions as in TGL, JSL, XEON_SP FSP header doesn't have
305 support for FSPS_ARCH_UPD.
307 config FSPS_USE_MULTI_PHASE_INIT
310 SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and
311 execute FspMultiPhaseSiInit() API.
313 config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
316 The FSP API is used to notify the FSP about different phases in the boot process.
317 The current FSP specification supports three notify phases:
318 - Post PCI enumeration
321 This option allows FSP to execute Notify Phase API (Post PCI enumeration).
322 SoC users can override this config to use coreboot native implementations
323 to perform the required lock down and chipset register configuration prior
324 to executing any 3rd-party code during PCI enumeration (i.e. Option ROM).
326 coreboot native implementation to skip FSP Notify Phase (Post PCI enumeration)
329 config USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
332 The FSP API is used to notify the FSP about different phases in the boot process.
333 The current FSP specification supports three notify phases:
334 - Post PCI enumeration
337 This option allows FSP to execute Notify Phase API (Ready to Boot).
338 SoC users can override this config to use coreboot native implementations
339 to perform the required lock down and chipset register configuration prior
342 config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
345 The FSP API is used to notify the FSP about different phases in the boot process.
346 The current FSP specification supports three notify phases:
347 - Post PCI enumeration
350 This option allows FSP to execute Notify Phase API (End of Firmware).
351 SoC users can override this config to use coreboot native implementations
352 to perform the required lock down and chipset register configuration prior
355 config FSP_USES_CB_DEBUG_EVENT_HANDLER
359 This option allows to create `Debug Event Handler` to print FSP debug messages
360 to output device using coreboot native implementation.
362 config DISPLAY_FSP_TIMESTAMPS
363 bool "Display FSP Timestamps"
366 Select this config to retrieve FSP timestamps from Firmware Performance Data Table
367 (FPDT) and display from ramstage after FSP-S is executed.
369 To be able to use this, FSP has to be compiled with `PcdFspPerformanceEnable` set to
372 config FSP_ENABLE_SERIAL_DEBUG
373 bool "Output FSP debug messages on serial console"
375 depends on FSP_USES_CB_DEBUG_EVENT_HANDLER
377 Output FSP debug messages on serial console.
379 The config option is selected based on your FSP configuration i.e., debug or
380 release. Enable this option from site-local to print FSP serial messages using
381 coreboot native debug driver when coreboot has integrated the debug FSP
382 binaries. coreboot disables serial messages when this config is not enabled.
384 config SAVE_MRC_AFTER_FSPS
387 depends on XEON_SP_COMMON_BASE
389 Save MRC training data after FSP-S. Select this on platforms that generate MRC
390 cache HOB data as part of FSP-S rather than FSP-M.