soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
[coreboot.git] / src / drivers / intel / fsp2_0 / fspt_report.c
blob7fa3205e3d0df36c883f2c5ca3326d53ad9b179c
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/symbols.h>
4 #include <console/console.h>
5 #include <fsp/util.h>
7 /* filled in assembly after FSP-T ran */
8 uintptr_t temp_memory_start;
9 uintptr_t temp_memory_end;
11 void report_fspt_output(void)
13 const struct region fsp_car_region = {
14 .offset = temp_memory_start,
15 .size = temp_memory_end - temp_memory_start,
17 const struct region coreboot_car_region = {
18 .offset = (uintptr_t)_car_region_start,
19 .size = (uintptr_t)_car_region_size,
21 printk(BIOS_DEBUG, "FSP-T: reported temp_mem region: [0x%08lx,0x%08lx)\n",
22 temp_memory_start, temp_memory_end);
23 if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) {
24 printk(BIOS_ERR, "Wrong CAR region used!\n");
25 printk(BIOS_ERR, "Adapt CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE to match FSP-T\n");